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* [X86][SSE] Share AVX1/AVX2 shuffle tests with AVX512 where possibleSimon Pilgrim2015-11-172-323/+504
| | | | llvm-svn: 253379
* [WinEH] Move WinEHFuncInfo from MachineModuleInfo to MachineFunctionReid Kleckner2015-11-172-6/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | Summary: Now that there is a one-to-one mapping from MachineFunction to WinEHFuncInfo, we don't need to use a DenseMap to select the right WinEHFuncInfo for the current funclet. The main challenge here is that X86WinEHStatePass is an IR pass that doesn't have access to the MachineFunction. I gave it its own WinEHFuncInfo object that it uses to calculate state numbers, which it then throws away. As long as nobody creates or removes EH pads between this pass and SDAG construction, we will get the same state numbers. The other thing X86WinEHStatePass does is to mark the EH registration node. Instead of communicating which alloca was the registration through WinEHFuncInfo, I added the llvm.x86.seh.ehregnode intrinsic. This intrinsic generates no code and simply marks the alloca in use. Reviewers: JCTremoulet Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D14668 llvm-svn: 253378
* [ARM] Don't pessimize i32 vselect.Charlie Turner2015-11-171-5/+6
| | | | | | | | | | | | | | | | | | The underlying issues surrounding codegen for 32-bit vselects have been resolved. The pessimistic costs for 64-bit vselects remain due to the bad scalarization that is still happening there. I tested this on A57 in T32, A32 and A64 modes. I saw no regressions, and some improvements. From my benchmarks, I saw these improvements in A57 (T32) spec.cpu2000.ref.177_mesa 5.95% lnt.SingleSource/Benchmarks/Shootout/strcat 12.93% lnt.MultiSource/Benchmarks/MiBench/telecomm-CRC32/telecomm-CRC32 11.89% I also measured A57 A32, A53 T32 and A9 T32 and found no performance regressions. I see much bigger wins in third-party benchmarks with this change Differential Revision: http://reviews.llvm.org/D14743 llvm-svn: 253349
* [AArch64] Promote f16 SELECT_CC CC operands when op is legal.Ahmed Bougacha2015-11-171-0/+27
| | | | | | | | | | | | | | | | SELECT_CC has the nasty property of having operands with unrelated types. So if you do something like: f32 = select_cc f16, f16, f32, f32, cc You'd only look for the action for <select_cc, f32>, but never f16. If the types are all legal, but the op isn't (as for f16 on AArch64, or for f128 on x86_64/AArch64?), then you get into trouble. For f128, we have softenSetCCOperands to handle this case. Similarly, for f16, we can directly promote the CC operands. llvm-svn: 253344
* Lower statepoints with multi-def targets.Pat Gavlin2015-11-171-1/+19
| | | | | | | | | | Statepoint lowering currently expects that the target method of a statepoint only defines a single value. This precludes using statepoints with ABIs that return values in multiple registers (e.g. the SysV AMD64 ABI). This change adds support for lowering statepoints with mutli-def targets. llvm-svn: 253339
* Use TargetRegisterInfo for printing MachineOperand register commentsDan Gohman2015-11-178-10/+10
| | | | | | | | | | | | | | | | Several places in AsmPrinter.cpp print comments describing MachineOperand registers using MCRegisterInfo, which uses MCOperand-oriented names. This doesn't work for targets that use virtual registers exclusively, as WebAssembly does, since virtual registers are represented and printed differently. This patch preserves what seems to be the spirit of r229978, avoiding the use of TM.getSubtargetImpl(), while still using MachineOperand-oriented printing for MachineOperands. Differential Revision: http://reviews.llvm.org/D14709 llvm-svn: 253338
* [ARM] Match VABDL from log2 shuffles.Charlie Turner2015-11-171-0/+38
| | | | | | Differential Revision: http://reviews.llvm.org/D14664 llvm-svn: 253334
* AVX512 : regenerate the test file against trunk.Igor Breger2015-11-171-117/+478
| | | | | | Differential Revision: http://reviews.llvm.org/D14742 llvm-svn: 253321
* Drop prelink support.Rafael Espindola2015-11-177-18/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The way prelink used to work was * The compiler decides if a given section only has relocations that are know to point to the same DSO. If so, it names it .data.rel.ro.local<something>. * The static linker puts all of these together. * The prelinker program assigns addresses to each library and resolves the local relocations. There are many problems with this: * It is incompatible with address space randomization. * The information passed by the compiler is redundant. The linker knows if a given relocation is in the same DSO or not. If could sort by that if so desired. * There are newer ways of speeding up DSO (gnu hash for example). * Even if we want to implement this again in the compiler, the previous implementation is pretty broken. It talks about relocations that are "resolved by the static linker". If they are resolved, there are none left for the prelinker. What one needs to track is if an expression will require only dynamic relocations that point to the same DSO. At this point it looks like the prelinker is an historical curiosity. For example, fedora has retired it because it failed to build for two releases (http://pkgs.fedoraproject.org/cgit/prelink.git/commit/?id=eb43100a8331d91c801ee3dcdb0a0bb9babfdc1f) This patch removes support for it. That is, it stops printing the ".local" sections. llvm-svn: 253280
* [WebAssembly] Fix printing of global operandsDerek Schuff2015-11-171-0/+7
| | | | | | | | | | This was regressed in r252656 which wasn't quite NFC. Instead of using a custom instruction as before, use a pattern to select CONST_I32 for the global addrs. Differential Revision: http://reviews.llvm.org/D14587 llvm-svn: 253276
* [WebAssembly] Fix function return type printingDerek Schuff2015-11-161-0/+21
| | | | | | | | | | | Summary: Previously return type information for a function was derived from return dag nodes. But this didn't work for dags with != return node. So instead compute it directly from the LLVM function as is done for imports. Differential Revision: http://reviews.llvm.org/D14593 llvm-svn: 253251
* [WebAssembly] Reverse the order of operands for br_ifDerek Schuff2015-11-161-11/+11
| | | | | | | | | | | | Summary: This is to match the new version in the spec Reviewers: sunfish Subscribers: jfb, llvm-commits, dschuff Differential Revision: http://reviews.llvm.org/D14519 llvm-svn: 253249
* Find available scratch register to use in function prologue and epilogue as ↵Kit Barton2015-11-164-31/+366
| | | | | | | part of shrink wrapping. Phabricator: http://reviews.llvm.org/D13955 llvm-svn: 253247
* [WinEH] Don't let UnwindHelp alias the return addressReid Kleckner2015-11-162-0/+50
| | | | | | | | | | | On top of that, don't bother allocating and initializing UnwindHelp if we don't have any funclets. Currently we always use RBP as our frame pointer when funclets are present, so this change makes it impossible to come here without any fixed stack objects. Fixes PR25533. llvm-svn: 253245
* [mips] Disable code generation through FastISel for MIPS32R6.Vasileios Kalintiris2015-11-161-0/+27
| | | | | | | | | | Reviewers: dsanders Subscribers: llvm-commits, dsanders Differential Revision: http://reviews.llvm.org/D14708 llvm-svn: 253225
* [mips][ias] Remove spurious ';' from inline assembly test.Daniel Sanders2015-11-161-4/+4
| | | | | | | IAS will not emit it. NFC at the moment but will prevent a test failure once IAS is enabled. llvm-svn: 253210
* [mips][ias] Accept $31 or $ra in hf16call32.ll. IAS prints the latter.Daniel Sanders2015-11-161-14/+14
| | | | | | NFC at the moment, but it will prevent a test failure once IAS is enabled. llvm-svn: 253209
* [mips][ias] Allow whitespace after commas in inlineasm*.ll tests.Daniel Sanders2015-11-164-59/+59
| | | | | | | IAS always prints whitespace after a comma. NFC at the moment but this will prevent failures when IAS is enabled. llvm-svn: 253208
* Properly check if a CMPZ node is in fact comparing against zeroJames Molloy2015-11-161-0/+11
| | | | | | | | This was left implicit and never ever checked, which means we could have a CMPZ against some non-zero value and we were carrying on with BFI conversion regardless. Caught by Oliver Stannard using csmith; regression test added. llvm-svn: 253195
* AVX512: Implemented encoding and intrinsics for VMOVSHDUP/VMOVSLDUP ↵Igor Breger2015-11-163-0/+167
| | | | | | | | instructions. Differential Revision: http://reviews.llvm.org/D14322 llvm-svn: 253185
* Revert r253160.Igor Breger2015-11-153-167/+0
| | | | | | It broke layering violation. Reproducible with BUILD_SHARED_LIBS=ON. llvm-svn: 253163
* AVX512: Implemented encoding and intrinsics for VMOVSHDUP/VMOVSLDUP ↵Igor Breger2015-11-153-0/+167
| | | | | | | | instructions. Differential Revision: http://reviews.llvm.org/D14322 llvm-svn: 253160
* [WebAssembly] Make indentation consistent with the other testcases. NFC.Dan Gohman2015-11-142-14/+14
| | | | llvm-svn: 253149
* [WebAssembly] Support signext, zeroext, and several other function attributes.Dan Gohman2015-11-141-0/+76
| | | | llvm-svn: 253148
* [WebAssembly] Change int_wasm_memory_size from IntrNoMem to IntrReadMem.Dan Gohman2015-11-142-2/+2
| | | | llvm-svn: 253147
* [X86][SSE] Fixed arch/triple and regenerated results.Simon Pilgrim2015-11-142-21/+75
| | | | | | Tidyup before diffs from new patch. llvm-svn: 253144
* [X86][SSE] Added extra vector truncation testsSimon Pilgrim2015-11-141-0/+201
| | | | | | Baseline comparison to D14588 llvm-svn: 253132
* [ShrinkWrapping] Disable the optimization for functions with sanitize likeQuentin Colombet2015-11-141-0/+40
| | | | | | | | | | attribute. Even if the target supports shrink-wrapping, the prologue and epilogue must not move because a crash can happen anywhere and sanitizers need to be able to unwind from the PC of the crash. llvm-svn: 253116
* [WinEH] Fix ESP management with 32-bit __CxxFrameHandler3Reid Kleckner2015-11-133-8/+6
| | | | | | | | | | | | | | | The C++ EH personality automatically restores ESP from the C++ EH registration node after a catchret. I mistakenly thought it was like SEH, which does not restore ESP. It makes sense for C++ EH to differ from SEH here because SEH does not use funclets for catches, and does not allow catching inside of finally. C++ EH may need to unwind through multiple catch funclets and eventually catchret to some outer funclet. Therefore, the runtime has to keep track of which ESP to use with catchret, rather than having the compiler reload it manually. llvm-svn: 253084
* [X86][SSE] Combine UNPCKL with vector_shuffle into UNPCKH to save one ↵Cong Hou2015-11-132-15/+9
| | | | | | | | | | | | | | | | | | | instruction for sext from v16i8 to v16i16 and v8i16 to v8i32. This patch is enabling combining UNPCKL with vector_shuffle that moves the upper half of a vector into the lower half, into a UNPCKH instruction. For example: t2: v16i8 = vector_shuffle<8,9,10,11,12,13,14,15,u,u,u,u,u,u,u,u> t1, undef:v16i8 t3: v16i8 = X86ISD::UNPCKL undef:v16i8, t2 will be combined to: t3: v16i8 = X86ISD::UNPCKH undef:v16i8, t1 Differential revision: http://reviews.llvm.org/D14399 llvm-svn: 253067
* Add missing triple to WinEH test caseReid Kleckner2015-11-131-1/+1
| | | | llvm-svn: 253062
* [WinEH] Make UnwindHelp a fixed stack object allocated after XMM CSRsReid Kleckner2015-11-136-13/+71
| | | | | | | Now the offset of UnwindHelp in our EH tables and the offset that we store to in the prologue agree. llvm-svn: 253059
* [ARM] Replace ARMISD::RBIT with ISD::BITREVERSEJames Molloy2015-11-131-0/+11
| | | | | | ISD::BITREVERSE matches "rbit" completely, so remove ARMISD::RBIT and mark ISD::BITREVERSE as legal, adding a test for lowering. llvm-svn: 253047
* [mips][ias] Explicitly disable IAS on asm-large-immediate.ll.Daniel Sanders2015-11-131-1/+2
| | | | | | NFC at the moment but it will prevent a failure when IAS is enabled by default. llvm-svn: 253039
* [mips][ias] Replace invalid assembly insn in test since IAS parses inline ↵Daniel Sanders2015-11-131-2/+2
| | | | | | | | | assembly. This is NFC at the moment but will prevent this test from failing when IAS is the default. llvm-svn: 253033
* [AArch64] Check the expansion of BITREVERSE in regression testJames Molloy2015-11-131-2/+21
| | | | | | | | Something I missed from Hal's review, rightly pointed out by Ben Kramer - we should make sure the expansion is properly checked as it can be easy for bugs to creep in. I've checked the scalar i8 expansion here and the vector i8 expansion in a previous commit. llvm-svn: 253024
* [SDAG] Fix expansion of BITREVERSEJames Molloy2015-11-131-0/+45
| | | | | | | | | | Richard Trieu noted that UBSan detected an overflowing shift, and the obvious fix caused a crash. What was happening was that the shiftee (1U) was indeed too small for the possible range of shifts it had to handle, but also we were using "VT.getSizeInBits()" to get the maximum type bitwidth, but we wanted "VT.getScalarSizeInBits()" to get the vector lane size instead of the entire vector size. Use an APInt for the shift and VT.getScalarSizeInBits(). llvm-svn: 253023
* [WebAssembly] Inline asm support.Dan Gohman2015-11-131-0/+53
| | | | llvm-svn: 252997
* [WinEH] Find root frame correctly in CLR funcletsJoseph Tremoulet2015-11-131-9/+27
| | | | | | | | | | | | | | | | | | | | | | | | | | Summary: The value that the CoreCLR personality passes to a funclet for the establisher frame may be the root function's frame or may be the parent funclet's (mostly empty) frame in the case of nested funclets. Each funclet stores a pointer to the root frame in its own (mostly empty) frame, as does the root function itself. All frames allocate this slot at the same offset, measured from the post-prolog stack pointer, so that the same sequence can accept any ancestor as an establisher frame parameter value, and so that a single offset can be reported to the GC, which also looks at this slot. This change allocate the slot when processing function entry, and records its frame index on the WinEHFuncInfo object, then inserts the code to set/copy it during prolog emission. Reviewers: majnemer, AndyAyers, pgavlin, rnk Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D14614 llvm-svn: 252983
* [WebAssembly] Introduce a new pseudo-operand for unused expression results.Dan Gohman2015-11-131-0/+9
| | | | llvm-svn: 252975
* X86-FMA3: Implemented commute transformations FMA*_Int instructions.Vyacheslav Klochkov2015-11-132-48/+303
| | | | | | | | | | It made it possible to apply the memory folding optimization for the 2nd operand of FMA*_Int instructions. Reviewer: Quentin Colombet Differential Revision: http://reviews.llvm.org/D14550 llvm-svn: 252973
* specify triple and tighten checks using update_llc_test_checks.pySanjay Patel2015-11-121-61/+62
| | | | llvm-svn: 252962
* Revert "Remove unnecessary call to getAllocatableRegClass"Tom Stellard2015-11-122-3/+3
| | | | | | | | | | | | | This reverts commit r252565. This also includes the revert of the commit mentioned below in order to avoid breaking tests in AMDGPU: Revert "AMDGPU: Set isAllocatable = 0 on VS_32/VS_64" This reverts commit r252674. llvm-svn: 252956
* [ShrinkWrap] Make sure we do not mess up with EH funclet lowering.Quentin Colombet2015-11-121-1/+3
| | | | | | | | ShrinkWrapping does not understand exception handling constraints for now, so make sure we do not mess with them by aborting on functions that use EH funclets. llvm-svn: 252917
* [WebAssembly] Reapply r252858, with svn add for the new file.Dan Gohman2015-11-1229-901/+623
| | | | | | | | | | | | | | | | | | | | | | Switch to MC for instruction printing. This encompasses several changes which are all interconnected: - Use the MC framework for printing almost all instructions. - AsmStrings are now live. - This introduces an indirection between LLVM vregs and WebAssembly registers, and a new pass, WebAssemblyRegNumbering, for computing a basic the mapping. This addresses some basic issues with argument registers and unused registers. - The way ARGUMENT instructions are handled no longer generates redundant get_local+set_local for every argument. This also changes the assembly syntax somewhat; most notably, MC's printing does not use sigils on label names, so those are no longer present, and push/pop now have a sigil to keep them unambiguous. The usage of set_local/get_local/$push/$pop will continue to evolve significantly. This patch is just one step of a larger change. llvm-svn: 252910
* Revert r252858: "[WebAssembly] Switch to MC for instruction printing."Hans Wennborg2015-11-1229-623/+901
| | | | | | | | It broke the CMake build: "Cannot find source file: WebAssemblyRegNumbering.cpp" llvm-svn: 252897
* [ARM] CMOV->BFI combining: handle both senses of CMPZJames Molloy2015-11-121-0/+11
| | | | | | | | I completely misunderstood what ARMISD::CMPZ means. It's not "compare equal to zero", it's "compare, only setting the zero/Z flag". It can either be equal-to-zero or not-equal-to-zero, and we weren't checking what sense it was. If it's equal-to-zero, we can swap the operands around and pretend like it is not-equal-to-zero, which is both a bug fix and lets us handle more cases. llvm-svn: 252891
* Revert "[ARM] Enable shrink-wrapping by default."Renato Golin2015-11-1211-27/+18
| | | | | | This reverts commit r252825, as it broke ASAN on ARM. Investigating... llvm-svn: 252889
* [SDAG] Introduce a new BITREVERSE node along with a corresponding LLVM intrinsicJames Molloy2015-11-123-0/+68
| | | | | | | | | | Several backends have instructions to reverse the order of bits in an integer. Conceptually matching such patterns is similar to @llvm.bswap, and it was mentioned in http://reviews.llvm.org/D14234 that it would be best if these patterns were matched in InstCombine instead of reimplemented in every different target. This patch introduces an intrinsic @llvm.bitreverse.i* that operates similarly to @llvm.bswap. For plumbing purposes there is also a new ISD node ISD::BITREVERSE, with simple expansion and promotion support. The intention is that InstCombine's BSWAP detection logic will be extended to support BITREVERSE too, and @llvm.bitreverse intrinsics emitted (if the backend supports lowering it efficiently). llvm-svn: 252878
* [WebAssembly] Switch to MC for instruction printing.Dan Gohman2015-11-1229-901/+623
| | | | | | | | | | | | | | | | | | | | This encompasses several changes which are all interconnected: - Use the MC framework for printing almost all instructions. - AsmStrings are now live. - This introduces an indirection between LLVM vregs and WebAssembly registers, and a new pass, WebAssemblyRegNumbering, for computing a basic the mapping. This addresses some basic issues with argument registers and unused registers. - The way ARGUMENT instructions are handled no longer generates redundant get_local+set_local for every argument. This also changes the assembly syntax somewhat; most notably, MC's printing use sigils on label names, so those are no longer present, and push/pop now have a sigil to keep them unambiguous. The usage of set_local/get_local/$push/$pop will continue to evolve significantly. This patch is just one step of a larger change. llvm-svn: 252858
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