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* test/CodeGen/X86/negative-sin.ll: FileCheck-ize.NAKAMURA Takumi2010-12-291-2/+2
| | | | llvm-svn: 122619
* test/CodeGen/X86/fp-in-intregs.ll: FileCheck-ize.NAKAMURA Takumi2010-12-291-1/+2
| | | | llvm-svn: 122618
* Radar 8803471: Fix expansion of ARM BCCi64 pseudo instructions.Bob Wilson2010-12-231-0/+1
| | | | | | | | If the basic block containing the BCCi64 (or BCCZi64) instruction ends with an unconditional branch, that branch needs to be deleted before appending the expansion of the BCCi64 to the end of the block. llvm-svn: 122521
* Fixes PR8823: add-with-overflow-128.llAndrew Trick2010-12-231-3/+1
| | | | | | | | In the bottom-up selection DAG scheduling, handle two-address instructions that read/write unspillable registers. Treat the entire chain of two-address nodes as a single live range. llvm-svn: 122472
* DAGCombine add (sext i1), X into sub X, (zext i1) if sext from i1 is ↵Benjamin Kramer2010-12-221-0/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | illegal. The latter usually compiles into smaller code. example code: unsigned foo(unsigned x, unsigned y) { if (x != 0) y--; return y; } before: _foo: ## @foo cmpl $1, 4(%esp) ## encoding: [0x83,0x7c,0x24,0x04,0x01] sbbl %eax, %eax ## encoding: [0x19,0xc0] notl %eax ## encoding: [0xf7,0xd0] addl 8(%esp), %eax ## encoding: [0x03,0x44,0x24,0x08] ret ## encoding: [0xc3] after: _foo: ## @foo cmpl $1, 4(%esp) ## encoding: [0x83,0x7c,0x24,0x04,0x01] movl 8(%esp), %eax ## encoding: [0x8b,0x44,0x24,0x08] adcl $-1, %eax ## encoding: [0x83,0xd0,0xff] ret ## encoding: [0xc3] llvm-svn: 122455
* X86: Lower a select directly to a setcc_carry if possible.Benjamin Kramer2010-12-221-2/+19
| | | | | | | | | | | | | | | | | | int test(unsigned long a, unsigned long b) { return -(a < b); } compiles to _test: ## @test cmpq %rsi, %rdi ## encoding: [0x48,0x39,0xf7] sbbl %eax, %eax ## encoding: [0x19,0xc0] ret ## encoding: [0xc3] instead of _test: ## @test xorl %ecx, %ecx ## encoding: [0x31,0xc9] cmpq %rsi, %rdi ## encoding: [0x48,0x39,0xf7] movl $-1, %eax ## encoding: [0xb8,0xff,0xff,0xff,0xff] cmovael %ecx, %eax ## encoding: [0x0f,0x43,0xc1] ret ## encoding: [0xc3] llvm-svn: 122451
* ptx: add ld instruction and testChe-Liang Chiou2010-12-221-0/+44
| | | | llvm-svn: 122398
* Fix a bug in ReduceLoadWidth that wasn't handling extendingChris Lattner2010-12-221-3/+21
| | | | | | | | | | | | | | | | | | | | | loads properly. We miscompiled the testcase into: _test: ## @test movl $128, (%rdi) movzbl 1(%rdi), %eax ret Now we get a proper: _test: ## @test movl $128, (%rdi) movsbl (%rdi), %eax movzbl %ah, %eax ret This fixes PR8757. llvm-svn: 122392
* Reapply 122353-122355 with fixes. 122354 was wrong;Dale Johannesen2010-12-212-3/+13
| | | | | | | | the shift type was needed one place, the shift count type another. The transform in 123555 had the same problem. llvm-svn: 122366
* Add some x86 specific dagcombines for conditional increments.Benjamin Kramer2010-12-211-0/+89
| | | | | | | | | | | | | | | | | | | | | | | | | | | | (add Y, (sete X, 0)) -> cmp X, 1; adc 0, Y (add Y, (setne X, 0)) -> cmp X, 1; sbb -1, Y (sub (sete X, 0), Y) -> cmp X, 1; sbb 0, Y (sub (setne X, 0), Y) -> cmp X, 1; adc -1, Y for unsigned foo(unsigned a, unsigned b) { if (a == 0) b++; return b; } we now get: foo: cmpl $1, %edi movl %esi, %eax adcl $0, %eax ret instead of: foo: testl %edi, %edi sete %al movzbl %al, %eax addl %esi, %eax ret llvm-svn: 122364
* Revert 122353-122355 for the moment, they broke stuff.Dale Johannesen2010-12-212-13/+3
| | | | llvm-svn: 122360
* Add a new transform to DAGCombiner.Dale Johannesen2010-12-211-0/+10
| | | | llvm-svn: 122355
* Get the type of a shift from the shift, not from its shiftDale Johannesen2010-12-211-3/+3
| | | | | | | | count operand. These should be the same but apparently are not always, and this is cleaner anyway. This improves the code in an existing test. llvm-svn: 122354
* Add ARM-specific DAG combining to cast i64 vector element load/stores to f64.Bob Wilson2010-12-211-0/+30
| | | | | | | | | | | Type legalization splits up i64 values into pairs of i32 values, which leads to poor quality code when inserting or extracting i64 vector elements. If the vector element is loaded or stored, it can be treated as an f64 value and loaded or stored directly from a VPR register. Use the pre-legalization DAG combiner to cast those vector elements to f64 types so that the type legalizer won't mess them up. Radar 8755338. llvm-svn: 122319
* Cosmetic changes.Dale Johannesen2010-12-201-1/+1
| | | | llvm-svn: 122259
* temporarily disable this: PR8823.Chris Lattner2010-12-201-17/+11
| | | | llvm-svn: 122222
* now that addc/adde are gone, "ADDC" in the X86 backend uses EFLAGS results,Chris Lattner2010-12-201-0/+19
| | | | | | | | | | | | | | | | | | | | | | | | the same as setcc. Optimize ADDC(0,0,FLAGS) -> SET_CARRY(FLAGS). This is a step towards finishing off PR5443. In the testcase in that bug we now get: movq %rdi, %rax addq %rsi, %rax sbbq %rcx, %rcx testb $1, %cl setne %dl ret instead of: movq %rdi, %rax addq %rsi, %rax movl $0, %ecx adcq $0, %rcx testq %rcx, %rcx setne %dl ret llvm-svn: 122219
* We lower setb to sbb with the hope that the and will go away, when it Chris Lattner2010-12-201-0/+9
| | | | | | | | | | | | | | | | | | | | | doesn't, match it back to setb. On a 64-bit version of the testcase before we'd get: movq %rdi, %rax addq %rsi, %rax sbbb %dl, %dl andb $1, %dl ret now we get: movq %rdi, %rax addq %rsi, %rax setb %dl ret llvm-svn: 122217
* Add comment for testcase for 122206Mon P Wang2010-12-201-1/+2
| | | | llvm-svn: 122210
* Prevents PerformShuffleCombine from creating a node with an illegal type ↵Mon P Wang2010-12-191-4/+24
| | | | | | | | after legalize types has run, e.g., prevent creating an i64 node from a v2i64 when i64 is not a legal type. llvm-svn: 122206
* improve the setcc -> setcc_carry optimization to happen moreChris Lattner2010-12-193-23/+34
| | | | | | | | consistently by moving it out of lowering into dag combine. Add some missing patterns for matching away extended versions of setcc_c. llvm-svn: 122201
* now that generic vector types aren't selected onto MMX registers, theseChris Lattner2010-12-1938-38/+36
| | | | | | tests don't need -disable-mmx. llvm-svn: 122188
* add a general coverage test for overflow intrinsics.Chris Lattner2010-12-191-0/+220
| | | | llvm-svn: 122185
* fix PR8642: if a critical edge has a PHI value that can trap,Chris Lattner2010-12-191-0/+29
| | | | | | | isel is *required* to split the edge. PHI values get evaluated on the edge, not in their predecessor block. llvm-svn: 122170
* move this test into the ARM test so that it is only run when the arm backendChris Lattner2010-12-191-0/+23
| | | | | | is enabled. llvm-svn: 122163
* Restore the behavior of frame lowering before my refactoring.Anton Korobeynikov2010-12-181-0/+22
| | | | | | | | It turns out that ppc backend has really weird interdependencies over different hooks and all stuff is fragile wrt small changes. This should fix PR8749 llvm-svn: 122155
* Just rename the functions, relying on matching a instruction that has the ↵Benjamin Kramer2010-12-181-4/+4
| | | | | | same name as a symbol is way too fragile. llvm-svn: 122154
* Test more than just label names and make test work on non-x86 hosts.Benjamin Kramer2010-12-181-1/+5
| | | | llvm-svn: 122153
* Fix result type of Neon floating-point comparisons against zero.Bob Wilson2010-12-181-0/+19
| | | | | | The result vector elements are always integers. Radar 8782191. llvm-svn: 122112
* During local stack slot allocation, the materializeFrameBaseRegister functionBill Wendling2010-12-171-0/+15
| | | | | | | | | | | | | | | may be called. If the entry block is empty, the insertion point iterator will be the "end()" value. Calling ->getParent() on it (among others) causes problems. Modify materializeFrameBaseRegister to take the machine basic block and insert the frame base register at the beginning of that block. (It's very similar to what the code does all ready. The only difference is that it will always insert at the beginning of the entry block instead of after a previous materialization of the frame base register. I doubt that that matters here.) <rdar://problem/8782198> llvm-svn: 122104
* Fix a DAGCombiner crash when folding binary vector operations with constantBob Wilson2010-12-171-0/+14
| | | | | | | BUILD_VECTOR operands where the element type is not legal. I had previously changed this code to insert TRUNCATE operations, but that was just wrong. llvm-svn: 122102
* Combine several vector-related DAGCombiner tests.Bob Wilson2010-12-175-61/+63
| | | | llvm-svn: 122101
* Add support for matching psign & plendvb to the x86 targetNate Begeman2010-12-171-0/+26
| | | | | | Remove unnecessary pandn patterns, 'vnot' patfrag looks through bitcasts llvm-svn: 122098
* Add a transform to DAG Combiner. This improves theDale Johannesen2010-12-171-0/+9
| | | | | | | code for the case where 32-bit divide by constant is turned into 64-bit multiply by constant. 8771012. llvm-svn: 122090
* Don't feed 19 bit immediates to ILA.Kalle Raiskila2010-12-171-2/+13
| | | | | | Patch (slightly modified) by Visa Putkinen. llvm-svn: 122052
* Fix crash compiling a QQQQ REG_SEQUENCE for a Neon vld3_lane operation.Bob Wilson2010-12-171-0/+19
| | | | | | Radar 8776599 llvm-svn: 122018
* 1. ARM/MC/ELF: A few more ELF relocs for .oJason W Kim2010-12-161-0/+35
| | | | | | | 2. Fixed EmitLocalCommonSymbol for ELF (Yes, they exist. :) Test added. llvm-svn: 121951
* Thumb1 had two patterns for the same load-from-constant-pool instruction.Jim Grosbach2010-12-151-3/+3
| | | | | | Canonicalize on tLDRpci and remove tLDRcp. llvm-svn: 121920
* Don't handle -arm-long-calls in fast isel for now.Eric Christopher2010-12-151-0/+30
| | | | llvm-svn: 121919
* Teach machine cse to commute instructions.Evan Cheng2010-12-151-0/+40
| | | | llvm-svn: 121903
* Add Neon VCVT instructions for f32 <-> f16 conversions.Bob Wilson2010-12-151-1/+19
| | | | | | | Clang is now providing intrinsics for these and so we need to support them in the backend. Radar 8068427. llvm-svn: 121902
* Lower the MBlaze target specific calling conventions for "interrupt_handler"Wesley Peck2010-12-152-0/+128
| | | | | | | and "save_volatiles" correctly. This completes the custom calling convention functionality changes for the MBlaze backend that were started in 121888. llvm-svn: 121891
* take care of some todos, transforming [us]mul_lohi into Chris Lattner2010-12-151-0/+1
| | | | | | a wider mul if the wider mul is legal. llvm-svn: 121848
* merge two testsChris Lattner2010-12-152-7/+10
| | | | llvm-svn: 121847
* Fix a minor bug in two-address pass. It was missing a commute opportunity.Evan Cheng2010-12-141-5/+43
| | | | | | | | | | | | | | | | | | | regB = move RCX regA = op regB, regC RAX = move regA where both regB and regC are killed. If regB is constrainted to non-compatible physical registers but regC is not constrainted at all, then it's better to commute the instruction. movl %edi, %eax shlq $32, %rcx leaq (%rcx,%rax), %rax => movl %edi, %eax shlq $32, %rcx orq %rcx, %rax rdar://8762995 llvm-svn: 121793
* bfi A, (and B, C1), C2) -> bfi A, B, C2 iff C1 & C2 == C1. rdar://8458663Evan Cheng2010-12-141-0/+13
| | | | llvm-svn: 121746
* fix fixme case typo :-) Jason W Kim2010-12-141-1/+1
| | | | llvm-svn: 121743
* First cut of ARM/MC/ELF PIC relocations.Jason W Kim2010-12-131-0/+100
| | | | | | Test has fixme, to move to .s -> .o test when AsmParser works better. llvm-svn: 121732
* Remove the rest of the *_sfp Neon instruction patterns.Bob Wilson2010-12-131-5/+0
| | | | | | | | | | | | | Use the same COPY_TO_REGCLASS approach as for the 2-register *_sfp instructions. This change made a big difference in the code generated for the CodeGen/Thumb2/cross-rc-coalescing-2.ll test: The coalescer is still doing a fine job, but some instructions that were previously moved outside the loop are not moved now. It's using fewer VFP registers now, which is generally a good thing, so I think the estimates for register pressure changed and that affected the LICM behavior. Since that isn't obviously wrong, I've just changed the test file. This completes the work for Radar 8711675. llvm-svn: 121730
* rename testChris Lattner2010-12-131-0/+0
| | | | llvm-svn: 121697
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