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* Remove 'llvm.x86.avx2.vbroadcasti128' intrinsic.Juergen Ributzka2015-03-042-7/+18
| | | | | | | | | | | The intrinsic is no longer generated by the front-end. Remove the intrinsic and auto-upgrade it to a vector shuffle. Reviewed by Nadav This is related to rdar://problem/18742778. llvm-svn: 231182
* Update twoaddr-coalesce-3.ll to run on darwin and linux machines:Eric Christopher2015-03-031-4/+5
| | | | | | | a) Default relocation model differences, b) Different numbers of # in comments llvm-svn: 231178
* WinEH: Remove vestigial EH objectReid Kleckner2015-03-035-10/+0
| | | | | | | | Ultimately, we'll need to leave something behind to indicate which alloca will hold the exception, but we can figure that out when it comes time to emit the __CxxFrameHandler3 catch handler table. llvm-svn: 231164
* Moving WinEH outlining tests to an architecture neutral locationAndrew Kaylor2015-03-037-0/+12
| | | | llvm-svn: 231155
* Fix a problem where the TwoAddressInstructionPass which generate redundant ↵Eric Christopher2015-03-031-0/+84
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | register moves in a loop. From: int M, total; void foo() { int i; for (i = 0; i < M; i++) { total = total + i / 2; } } This is the kernel loop: .LBB0_2: # %for.body =>This Inner Loop Header: Depth=1 movl %edx, %esi movl %ecx, %edx shrl $31, %edx addl %ecx, %edx sarl %edx addl %esi, %edx incl %ecx cmpl %eax, %ecx jl .LBB0_2 -------------------------- The first mov insn "movl %edx, %esi" could be removed if we change "addl %esi, %edx" to "addl %edx, %esi". The IR before TwoAddressInstructionPass is: BB#2: derived from LLVM BB %for.body Predecessors according to CFG: BB#1 BB#2 %vreg3<def> = COPY %vreg12<kill>; GR32:%vreg3,%vreg12 %vreg2<def> = COPY %vreg11<kill>; GR32:%vreg2,%vreg11 %vreg7<def,tied1> = SHR32ri %vreg3<tied0>, 31, %EFLAGS<imp-def,dead>; GR32:%vreg7,%vreg3 %vreg8<def,tied1> = ADD32rr %vreg3<tied0>, %vreg7<kill>, %EFLAGS<imp-def,dead>; GR32:%vreg8,%vreg3,%vreg7 %vreg9<def,tied1> = SAR32r1 %vreg8<kill,tied0>, %EFLAGS<imp-def,dead>; GR32:%vreg9,%vreg8 %vreg4<def,tied1> = ADD32rr %vreg9<kill,tied0>, %vreg2<kill>, %EFLAGS<imp-def,dead>; GR32:%vreg4,%vreg9,%vreg2 %vreg5<def,tied1> = INC64_32r %vreg3<kill,tied0>, %EFLAGS<imp-def,dead>; GR32:%vreg5,%vreg3 CMP32rr %vreg5, %vreg0, %EFLAGS<imp-def>; GR32:%vreg5,%vreg0 %vreg11<def> = COPY %vreg4; GR32:%vreg11,%vreg4 %vreg12<def> = COPY %vreg5<kill>; GR32:%vreg12,%vreg5 JL_4 <BB#2>, %EFLAGS<imp-use,kill> Now TwoAddressInstructionPass will choose vreg9 to be tied with vreg4. However, it doesn't see that there is copy from vreg4 to vreg11 and another copy from vreg11 to vreg2 inside the loop body. To remove those copies, it is necessary to choose vreg2 to be tied with vreg4 instead of vreg9. This code pattern commonly appears when there is reduction operation in a loop. So check for a reversed copy chain and if we encounter one then we can commute the add instruction so we can avoid a copy. Patch by Wei Mi. http://reviews.llvm.org/D7806 llvm-svn: 231148
* Outline cleanup handlers for native Windows C++ exception handlingAndrew Kaylor2015-03-036-14/+106
| | | | | | Differential Revision: http://reviews.llvm.org/D7865 llvm-svn: 231117
* Add the following 64-bit vector integer arithmetic instructions added in POWER8:Kit Barton2015-03-035-0/+428
| | | | | | | | | | | | | | | | | | | | | | | | | | | | vaddudm vsubudm vmulesw vmulosw vmuleuw vmulouw vmuluwm vmaxsd vmaxud vminsd vminud vcmpequd vcmpequd. vcmpgtsd vcmpgtsd. vcmpgtud vcmpgtud. vrld vsld vsrd vsrad Phabricator review: http://reviews.llvm.org/D7959 llvm-svn: 231115
* Make llvm.eh.begincatch use an outparamReid Kleckner2015-03-035-66/+53
| | | | | | | | | | | | | | Ultimately, __CxxFrameHandler3 needs us to put a stack offset in a table, and it will take responsibility for copying the exception object into that slot. Modelling the exception object as an SSA value returned by begincatch isn't going to work in general, so make it use an output parameter. Reviewers: andrew.w.kaylor Differential Revision: http://reviews.llvm.org/D7920 llvm-svn: 231086
* [AArch64] When combining constant mul of -3, prefer (sub x, (shl x, N)).Chad Rosier2015-03-031-2/+1
| | | | | | This change only effects codegen when the constant is -3. llvm-svn: 231085
* DebugInfo: Move new hierarchy into placeDuncan P. N. Exon Smith2015-03-0355-1710/+1710
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Move the specialized metadata nodes for the new debug info hierarchy into place, finishing off PR22464. I've done bootstraps (and all that) and I'm confident this commit is NFC as far as DWARF output is concerned. Let me know if I'm wrong :). The code changes are fairly mechanical: - Bumped the "Debug Info Version". - `DIBuilder` now creates the appropriate subclass of `MDNode`. - Subclasses of DIDescriptor now expect to hold their "MD" counterparts (e.g., `DIBasicType` expects `MDBasicType`). - Deleted a ton of dead code in `AsmWriter.cpp` and `DebugInfo.cpp` for printing comments. - Big update to LangRef to describe the nodes in the new hierarchy. Feel free to make it better. Testcase changes are enormous. There's an accompanying clang commit on its way. If you have out-of-tree debug info testcases, I just broke your build. - `upgrade-specialized-nodes.sh` is attached to PR22564. I used it to update all the IR testcases. - Unfortunately I failed to find way to script the updates to CHECK lines, so I updated all of these by hand. This was fairly painful, since the old CHECKs are difficult to reason about. That's one of the benefits of the new hierarchy. This work isn't quite finished, BTW. The `DIDescriptor` subclasses are almost empty wrappers, but not quite: they still have loose casting checks (see the `RETURN_FROM_RAW()` macro). Once they're completely gutted, I'll rename the "MD" classes to "DI" and kill the wrappers. I also expect to make a few schema changes now that it's easier to reason about everything. llvm-svn: 231082
* During PHI elimination, split critical edges that move copies out of loops.Daniel Jasper2015-03-031-1/+38
| | | | | | | | | | | | | | | | | | | | This prevents the behavior observed in llvm.org/PR22369. I am not sure whether I am reading the code correctly, but the early exit based on isLiveOutPastPHIs() seems to make the wrong assumption that RegisterCoalescer won't be able to coalesce those copies later. This change hides the new behavior behind -no-phi-elim-live-out-early-exit as it currently breaks four tests: * Assertion in: CodeGen/Hexagon/hwloop-cleanup.ll * Worse code in: CodeGen/X86/coalescer-commute4.ll CodeGen/X86/phys_subreg_coalesce-2.ll CodeGen/X86/zlib-longest-match.ll The root cause here seems to be that the heuristic that determines the visitation order in RegisterCoalescer gets less lucky. llvm-svn: 231064
* [X86] Special-case 2x CMOV when custom-inserting.Ahmed Bougacha2015-03-031-109/+71
| | | | | | | | | | | | | | | | | | This lets us avoid a few copies that are otherwise hard to get rid of. The way this is done is, the custom-inserter looks at the following instruction for another CMOV, and replaces both at the same time. A previous version used a new CMOV2 opcode, but the custom inserter is expected to be able to return a different basic block anyway, which means it's OK - though far from ideal - to alter that block's contents. Explicitly document that, in case it ever makes a difference. Alternatives welcome! Follow-up to r231045. rdar://19767934 Closes http://reviews.llvm.org/D8019 llvm-svn: 231046
* [X86] Combine (cmov (and/or (setcc) (setcc))) into (cmov (cmov)).Ahmed Bougacha2015-03-032-10/+280
| | | | | | | | | | | | | | | | | | | Fold and/or of setcc's to double CMOV: (CMOV F, T, ((cc1 | cc2) != 0)) -> (CMOV (CMOV F, T, cc1), T, cc2) (CMOV F, T, ((cc1 & cc2) != 0)) -> (CMOV (CMOV T, F, !cc1), F, !cc2) When we can't use the CMOV instruction, it might increase branch mispredicts. When we can, or when there is no mispredict, this improves throughput and reduces register pressure. These can't be catched by generic combines, because the pattern can appear when legalizing some instructions (such as fcmp une). rdar://19767934 http://reviews.llvm.org/D7634 llvm-svn: 231045
* Fix cppeh breakage due to racing commitsReid Kleckner2015-03-032-66/+66
| | | | llvm-svn: 231044
* Remap arguments and non-alloca values used by outlined C++ exception handlers.Andrew Kaylor2015-03-032-0/+445
| | | | | | Differential Revision: http://reviews.llvm.org/D7844 llvm-svn: 231042
* WinEH: Run opt -instnamer over some cppeh tests and update CHECKsReid Kleckner2015-03-033-86/+86
| | | | | | | | | In the future, we should run the output of clang through instnamer to make it easier to manually edit test cases. No functionality change. llvm-svn: 231037
* Refactor DebugLocDWARFExpression so it doesn't require access to theAdrian Prantl2015-03-022-5/+5
| | | | | | | | | | | | | | TargetRegisterInfo. DebugLocEntry now holds a buffer with the raw bytes of the pre-calculated DWARF expression. Ought to be NFC, but it does slightly alter the output format of the textual assembly. This reapplies 230930 without the assertion in DebugLocEntry::finalize() because not all Machine registers can be lowered into DWARF register numbers and floating point constants cannot be expressed. llvm-svn: 231023
* Revert "Refactor DebugLocDWARFExpression so it doesn't require access to the"Adrian Prantl2015-03-022-5/+5
| | | | | | This reverts commit 230975 to investigate buildbot breakage. llvm-svn: 231004
* Change SystemZ large tests to use the existing long_tests propertyDavid Blaikie2015-03-021-2/+2
| | | | | | | | | | (this is already used in Clang for a couple of tests) Reviewers: uweigand Differential Revision: http://reviews.llvm.org/D7965 llvm-svn: 230998
* Refactor DebugLocDWARFExpression so it doesn't require access to theAdrian Prantl2015-03-022-5/+5
| | | | | | | | | | | | | TargetRegisterInfo. DebugLocEntry now holds a buffer with the raw bytes of the pre-calculated DWARF expression. Ought to be NFC, but it does slightly alter the output format of the textual assembly. This reapplies 230930 with a relaxed assertion in DebugLocEntry::finalize() that allows for empty DWARF expressions for constant FP values. llvm-svn: 230975
* [mips] Optimize conditional moves where RHS is zero.Vasileios Kalintiris2015-03-021-175/+127
| | | | | | | | | | | | | Summary: When the RHS of a conditional move node is zero, we can utilize the $zero register by inverting the conditional move instruction and by swapping the order of its True/False operands. Reviewers: dsanders Differential Revision: http://reviews.llvm.org/D7945 llvm-svn: 230956
* Revert r230930, it caused PR22747.Nico Weber2015-03-022-5/+5
| | | | llvm-svn: 230932
* Refactor DebugLocDWARFExpression so it doesn't require access to theAdrian Prantl2015-03-022-5/+5
| | | | | | | | | | TargetRegisterInfo. DebugLocEntry now holds a buffer with the raw bytes of the pre-calculated DWARF expression. Ought to be NFC, but it does slightly alter the output format of the textual assembly. llvm-svn: 230930
* AVX-512: Added mask and rounding mode for scalar arithmeticsElena Demikhovsky2015-03-011-0/+92
| | | | | | Added more tests for scalar instructions to destinguish between AVX and AVX-512 forms. llvm-svn: 230891
* avoid infinite looping when folding vector multiplies of constants (PR22698)Sanjay Patel2015-03-011-0/+34
| | | | | | | | | | | | | | | We were missing a check for the following fold in DAGCombiner: // fold (fmul (fmul x, c1), c2) -> (fmul x, (fmul c1, c2)) If 'x' is also a constant, then we shouldn't do anything. Otherwise, we could end up swapping the operands back and forth forever. This should fix: http://llvm.org/bugs/show_bug.cgi?id=22698 Differential Revision: http://reviews.llvm.org/D7917 llvm-svn: 230884
* fixed to test only the feature, not the feature and a CPUSanjay Patel2015-03-011-3/+3
| | | | llvm-svn: 230883
* make the tested feature (SSE2) explicitSanjay Patel2015-02-281-1/+1
| | | | llvm-svn: 230881
* DebugInfo: Fix invalid file reference in CodeGen/X86/unknown-location.llDuncan P. N. Exon Smith2015-02-281-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There are two types of files in the old (current) debug info schema. !0 = !{!"some/filename", !"/path/to/dir"} !1 = !{!"0x29", !0} ; [ DW_TAG_file_type ] !1 has a wrapper class called `DIFile` which inherits from `DIScope` and is referenced in 'scope' fields. !0 is called a "file node", and debug info nodes with a 'file' field point at one of these directly -- although they're built in `DIBuilder` by sending in a `DIFile` and reaching into it. In the new hierarchy, I unified these nodes as `MDFile` (which `DIFile` is a lightweight wrapper for) in r230057. Moving the new hierarchy into place (and upgrading testcases) caused CodeGen/X86/unknown-location.ll to start failing -- apparently "0x29" was previously showing up in the linetable as a filename, causing: .loc 2 4 3 (where 2 points at filename "0x29") instead of: .loc 1 4 3 (where 1 points at the actual filename). Change the testcase to use the old schema correctly. llvm-svn: 230880
* fixed to test only the feature, not the feature and a CPUSanjay Patel2015-02-281-1/+1
| | | | llvm-svn: 230878
* [X86] Remove the blendpd/blendps/pblendw/pblendd intrinsics. They can ↵Craig Topper2015-02-284-44/+28
| | | | | | represented by shuffle_vector instructions. llvm-svn: 230860
* Regenerated test case from pr 230801 for change in LLVM IR syntaxBill Schmidt2015-02-271-0/+78
| | | | llvm-svn: 230811
* Update SystemZ/Large test generators to handle new gep IR syntaxDavid Blaikie2015-02-2714-27/+27
| | | | llvm-svn: 230810
* Update SystemZ/Large test generators to handle new load IR syntaxDavid Blaikie2015-02-2714-27/+27
| | | | llvm-svn: 230809
* Revert test case until it can be fixedBill Schmidt2015-02-271-65/+0
| | | | llvm-svn: 230803
* [PowerPC] Fix PR22711 - Misaligned .toc sectionBill Schmidt2015-02-271-0/+65
| | | | | | | | | | | | Straightforward patch to emit an alignment directive when emitting a TOC entry. The test case was generated from the test in PR22711 that demonstrated a misaligned .toc section. The object code is run through llvm-readobj to verify that the correct alignment has been applied to the .toc section. Thanks to Ulrich Weigand for running down where the fix was needed. llvm-svn: 230801
* [opaque pointer type] Add textual IR support for explicit type parameter to ↵David Blaikie2015-02-272572-22304/+22304
| | | | | | | | | | | | | | | | | | | | | | | | load instruction Essentially the same as the GEP change in r230786. A similar migration script can be used to update test cases, though a few more test case improvements/changes were required this time around: (r229269-r229278) import fileinput import sys import re pat = re.compile(r"((?:=|:|^)\s*load (?:atomic )?(?:volatile )?(.*?))(| addrspace\(\d+\) *)\*($| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$)") for line in sys.stdin: sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line)) Reviewers: rafael, dexonsmith, grosser Differential Revision: http://reviews.llvm.org/D7649 llvm-svn: 230794
* Target/X86: Never use the redzone for Win64 ABI functions.Charles Davis2015-02-271-1/+2
| | | | | | | | | | | | | | | | | Summary: Until now, we did this (among other things) based on whether or not the target was Windows. This is clearly wrong, not just for Win64 ABI functions on non-Windows, but for System V ABI functions on Windows, too. In this change, we make this decision based on the ABI the calling convention specifies instead. Reviewers: rnk Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D7953 llvm-svn: 230793
* [PowerPC] Use vector types for memcpy and friends (sometimes)Hal Finkel2015-02-272-2/+114
| | | | | | | | | | When using Altivec, we can use vector loads and stores for aligned memcpy and friends. Starting with the P7 and VXS, we have reasonable unaligned vector stores. Starting with the P8, we have fast unaligned loads too. For QPX, we use vector loads are stores, but only for aligned memory accesses. llvm-svn: 230788
* [opaque pointer type] Add textual IR support for explicit type parameter to ↵David Blaikie2015-02-271232-35505/+35505
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | getelementptr instruction One of several parallel first steps to remove the target type of pointers, replacing them with a single opaque pointer type. This adds an explicit type parameter to the gep instruction so that when the first parameter becomes an opaque pointer type, the type to gep through is still available to the instructions. * This doesn't modify gep operators, only instructions (operators will be handled separately) * Textual IR changes only. Bitcode (including upgrade) and changing the in-memory representation will be in separate changes. * geps of vectors are transformed as: getelementptr <4 x float*> %x, ... ->getelementptr float, <4 x float*> %x, ... Then, once the opaque pointer type is introduced, this will ultimately look like: getelementptr float, <4 x ptr> %x with the unambiguous interpretation that it is a vector of pointers to float. * address spaces remain on the pointer, not the type: getelementptr float addrspace(1)* %x ->getelementptr float, float addrspace(1)* %x Then, eventually: getelementptr float, ptr addrspace(1) %x Importantly, the massive amount of test case churn has been automated by same crappy python code. I had to manually update a few test cases that wouldn't fit the script's model (r228970,r229196,r229197,r229198). The python script just massages stdin and writes the result to stdout, I then wrapped that in a shell script to handle replacing files, then using the usual find+xargs to migrate all the files. update.py: import fileinput import sys import re ibrep = re.compile(r"(^.*?[^%\w]getelementptr inbounds )(((?:<\d* x )?)(.*?)(| addrspace\(\d\)) *\*(|>)(?:$| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$))") normrep = re.compile( r"(^.*?[^%\w]getelementptr )(((?:<\d* x )?)(.*?)(| addrspace\(\d\)) *\*(|>)(?:$| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$))") def conv(match, line): if not match: return line line = match.groups()[0] if len(match.groups()[5]) == 0: line += match.groups()[2] line += match.groups()[3] line += ", " line += match.groups()[1] line += "\n" return line for line in sys.stdin: if line.find("getelementptr ") == line.find("getelementptr inbounds"): if line.find("getelementptr inbounds") != line.find("getelementptr inbounds ("): line = conv(re.match(ibrep, line), line) elif line.find("getelementptr ") != line.find("getelementptr ("): line = conv(re.match(normrep, line), line) sys.stdout.write(line) apply.sh: for name in "$@" do python3 `dirname "$0"`/update.py < "$name" > "$name.tmp" && mv "$name.tmp" "$name" rm -f "$name.tmp" done The actual commands: From llvm/src: find test/ -name *.ll | xargs ./apply.sh From llvm/src/tools/clang: find test/ -name *.mm -o -name *.m -o -name *.cpp -o -name *.c | xargs -I '{}' ../../apply.sh "{}" From llvm/src/tools/polly: find test/ -name *.ll | xargs ./apply.sh After that, check-all (with llvm, clang, clang-tools-extra, lld, compiler-rt, and polly all checked out). The extra 'rm' in the apply.sh script is due to a few files in clang's test suite using interesting unicode stuff that my python script was throwing exceptions on. None of those files needed to be migrated, so it seemed sufficient to ignore those cases. Reviewers: rafael, dexonsmith, grosser Differential Revision: http://reviews.llvm.org/D7636 llvm-svn: 230786
* Remove the Forward Control Flow Integrity pass and its dependencies.Eric Christopher2015-02-279-499/+1
| | | | | | | | | This work is currently being rethought along different lines and if this work is needed it can be resurrected out of svn. Remove it for now as no current work in ongoing on it and it's unused. Verified with the authors before removal. llvm-svn: 230780
* Change the fast-isel-abort option from bool to int to enable "levels"Mehdi Amini2015-02-27142-265/+265
| | | | | | | | | | | | | | | | | | | | | | | Summary: Currently fast-isel-abort will only abort for regular instructions, and just warn for function calls, terminators, function arguments. There is already fast-isel-abort-args but nothing for calls and terminators. This change turns the fast-isel-abort options into an integer option, so that multiple levels of strictness can be defined. This will help no being surprised when the "abort" option indeed does not abort, and enables the possibility to write test that verifies that no intrinsics are forgotten by fast-isel. Reviewers: resistor, echristo Subscribers: jfb, llvm-commits Differential Revision: http://reviews.llvm.org/D7941 From: Mehdi Amini <mehdi.amini@apple.com> llvm-svn: 230775
* Centralize handling of the eh_begin and eh_end labels.Rafael Espindola2015-02-275-7/+33
| | | | | | | | | | This removes a bit of duplicated code and more importantly, remembers the labels so that they don't need to be looked up by name. This in turn allows for any name to be used and avoids a crash if the name we wanted was already taken. llvm-svn: 230772
* Equally to NetBSD, Bitrig/ARM uses the Itanium-ABI.Renato Golin2015-02-271-0/+4
| | | | | | Patch by Patrick Wildt. llvm-svn: 230762
* [mips][microMIPS] Change register class for GP registerZoran Jovanovic2015-02-271-0/+18
| | | | | | Differential Revision: http://reviews.llvm.org/D7934 llvm-svn: 230760
* Pass correct -mtriple for krait-cpu-div-attribute.llPetar Jovanovic2015-02-271-1/+1
| | | | | | | | | Not passing mtriple for one of the tests caused a regression failure on MIPS buildbot. The issue was introduced by r230651. Differential Revision: http://reviews.llvm.org/D7938 llvm-svn: 230756
* [x86] Run most of the rest of the shuffle combining over non-128-bitChandler Carruth2015-02-272-55/+18
| | | | | | | | | | | | vectors. This lets us fix the rest of the v16 lowering problems when pshufb is clearly better. We might still be able to improve some of the lowerings by enabling the other combine-based rewriting to fire for non-128-bit vectors, but this at least should remove any regressions from using the fancy v16i16 lowering strategy. llvm-svn: 230753
* [x86] Teach a bunch of the x86-specific shuffle combining to work withChandler Carruth2015-02-271-2/+1
| | | | | | | 256-bit vectors as well as 128-bit vectors. Fixes some of the redundant shuffles for v16i16. llvm-svn: 230752
* [x86] Make the v8i16 clever single-input shuffle lowering usable forChandler Carruth2015-02-272-34/+86
| | | | | | | | | | | | | | | | | repeated 128-bit lane shuffles of wider vector types and use it to lower 256-bit v16i16 vector shuffles where applicable. This should let us perfectly lowering the pattern of pshuflw and pshufhw even for AVX2 256-bit patterns. I've not added AVX-512 support, but it should be trivial for someone working on that to wire up. Note that currently this generates bad, long shuffle chains because we don't combine 256-bit target shuffles. The subsequent patches will fix that. llvm-svn: 230751
* [x86] Add a bunch more tests for v16i16 shuffles. All of these are takenChandler Carruth2015-02-271-0/+1669
| | | | | | | | by mirroring v8i16 test cases across both 128-bit lanes. This should highlight problems where we aren't correctly using 128-bit shuffles to implement things. llvm-svn: 230750
* [mips] Account for constant-zero operands in ADDE nodes.Vasileios Kalintiris2015-02-271-0/+35
| | | | | | | | | | | | | | | Summary: We identify the cases where the operand to an ADDE node is a constant zero. In such cases, we can avoid generating an extra ADDu instruction disguised as an identity move alias (ie. addu $r, $r, 0 --> move $r, $r). Reviewers: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D7906 llvm-svn: 230742
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