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* [globalisel][irtranslator] Fix test from r345743 on non-asserts builds.Daniel Sanders2018-10-311-0/+2
| | | | llvm-svn: 345754
* [globalisel][irtranslator] Verify that DILocations aren't lost in translationDaniel Sanders2018-10-311-0/+51
| | | | | | | | | | | | | | | | Summary: Also fix a couple bugs where DILocations are lost. EntryBuilder wasn't passing on debug locations for PHI's, constants, GLOBAL_VALUE, etc. Reviewers: aprantl, vsk, bogner, aditya_nandakumar, volkan, rtereshin, aemerson Reviewed By: aemerson Subscribers: aemerson, rovka, kristof.beyls, javed.absar, llvm-commits Differential Revision: https://reviews.llvm.org/D53740 llvm-svn: 345743
* MachineModuleInfo: Initialize DbgInfoAvailable depending on debug_cus existingMatthias Braun2018-10-311-0/+26
| | | | | | | | | | | | | | | | Before this patch DbgInfoAvailable was set to true in DwarfDebug::beginModule() or CodeViewDebug::CodeViewDebug(). This made MIR testing weird since passes would suddenly stop dealing with debug info just because we stopped the pipeline before the debug printers. This patch changes the logic to initialize DbgInfoAvailable based on the fact that debug_compile_units exist in the llvm Module. The debug printers may then override it with false in case of debug printing being disabled. Differential Revision: https://reviews.llvm.org/D53885 llvm-svn: 345740
* [Hexagon] Make sure not to use GP-relative addressing with PICKrzysztof Parzyszek2018-10-311-0/+37
| | | | | | | Make sure that -relocation-model=pic prevents use of GP-relative addressing modes. llvm-svn: 345731
* [DAGCombiner] Fold 0 div/rem X to 0David Bolvansky2018-10-314-275/+19
| | | | | | | | | | | | Reviewers: RKSimon, spatel, javed.absar, craig.topper, t.p.northover Reviewed By: RKSimon Subscribers: craig.topper, llvm-commits Differential Revision: https://reviews.llvm.org/D52504 llvm-svn: 345721
* AMDGPU: Rewrite SILowerI1Copies to always stay on SALUNicolai Haehnle2018-10-3115-141/+264
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: Instead of writing boolean values temporarily into 32-bit VGPRs if they are involved in PHIs or are observed from outside a loop, we use bitwise masking operations to combine lane masks in a way that is consistent with wave control flow. Move SIFixSGPRCopies to before this pass, since that pass incorrectly attempts to move SGPR phis to VGPRs. This should recover most of the code quality that was lost with the bug fix in "AMDGPU: Remove PHI loop condition optimization". There are still some relevant cases where code quality could be improved, in particular: - We often introduce redundant masks with EXEC. Ideally, we'd have a generic computeKnownBits-like analysis to determine whether masks are already masked by EXEC, so we can avoid this masking both here and when lowering uniform control flow. - The criterion we use to determine whether a def is observed from outside a loop is conservative: it doesn't check whether (loop) branch conditions are uniform. Change-Id: Ibabdb373a7510e426b90deef00f5e16c5d56e64b Reviewers: arsenm, rampitec, tpr Subscribers: kzhuravl, jvesely, wdng, mgorny, yaxunl, dstuttard, t-tye, eraman, llvm-commits Differential Revision: https://reviews.llvm.org/D53496 llvm-svn: 345719
* AMDGPU: Remove PHI loop condition optimizationNicolai Haehnle2018-10-314-79/+74
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: The optimization to early break out of loops if all threads are dead was never fully implemented. But the PHI node analyzing is actually causing a number of problems, so remove all the extra code for it. (This does actually regress code quality in a few places because it ends up relying more heavily on phi's of i1, which we don't do a great job with. However, since it fixes real bugs in the wild, we should take this change. I have some prototype changes to improve i1 lowering in general -- not just for control flow -- which should help recover the code quality, I just need to make those changes fit for general consumption. -- Nicolai) Change-Id: I6fc6c6c8961857ac6009fcfb9f7e5e48dc23fbb1 Patch-by: Christian König <christian.koenig@amd.com> Reviewers: arsenm, rampitec, tpr Subscribers: kzhuravl, jvesely, wdng, yaxunl, dstuttard, t-tye, llvm-commits Differential Revision: https://reviews.llvm.org/D53359 llvm-svn: 345718
* [AMDGPU] support image load/store a16Neil Henning2018-10-315-0/+1054
| | | | | | | | | | | | Our a16 support was only enabled for sample/gather and buffer load/store, but not for image load/store operations (which take an i16 as the pixel index rather than a half). Fix our isel lowering and add test cases to prove it out. Differential Revision: https://reviews.llvm.org/D53750 llvm-svn: 345710
* [ARM64] [Windows] Exception handling support in frame loweringSanjin Sijaric2018-10-3111-35/+943
| | | | | | | | | | Emit pseudo instructions indicating unwind codes corresponding to each instruction inside the prologue/epilogue. These are used by the MCLayer to populate the .xdata section. Differential Revision: https://reviews.llvm.org/D50288 llvm-svn: 345701
* [AArch64] Mark condition flags and x16/x17 as clobbered when calling __chkstkMartin Storsjo2018-10-311-0/+8
| | | | | | | | This is similar to SVN r311061 for ARM. Differential Revision: https://reviews.llvm.org/D53878 llvm-svn: 345698
* MachineOperand/MIParser: Do not print debug-use flag, infer itMatthias Braun2018-10-3026-106/+110
| | | | | | | | | | | | | | The debug-use flag must be set exactly for uses on DBG_VALUEs. This is so obvious that it can be trivially inferred while parsing. This will reduce noise when printing while omitting an information that has little value to the user. The parser will keep recognizing the flag for compatibility with old `.mir` files. Differential Revision: https://reviews.llvm.org/D53903 llvm-svn: 345671
* [ARM][NFC] Make tests immune to better div optimizationsDavid Bolvansky2018-10-303-18/+16
| | | | | | | | | | | | | | Summary: Related to D52504 Reviewers: spatel Reviewed By: spatel Subscribers: javed.absar, kristof.beyls, chrib, llvm-commits Differential Revision: https://reviews.llvm.org/D53901 llvm-svn: 345665
* Revert r345542: AMDGPU: Enable code object v3 by defaultKonstantin Zhuravlyov2018-10-3033-120/+120
| | | | | | It breaks mesa. llvm-svn: 345662
* [FPEnv] [FPEnv] Add constrained intrinsics for MAXNUM and MINNUMCameron McInally2018-10-301-0/+519
| | | | | | Differential Revision: https://reviews.llvm.org/D53216 llvm-svn: 345650
* [x86] try to make test immune to better div optimization; NFCISanjay Patel2018-10-301-25/+18
| | | | llvm-svn: 345642
* [COFF, ARM64] Make sure to forward arguments from vararg to musttail varargMandeep Singh Grang2018-10-301-0/+34
| | | | | | | | | | | | | | | | | | Summary: Thunk functions in Windows are varag functions that call a musttail function to pass the arguments after the fixup is done. We need to make sure that we forward the arguments from the caller vararg to the callee vararg function. This is the same mechanism that is used for Windows on X86. Reviewers: ssijaric, eli.friedman, TomTan, mgrang, mstorsjo, rnk, compnerd, efriedma Reviewed By: efriedma Subscribers: efriedma, kristof.beyls, chrib, javed.absar, llvm-commits Differential Revision: https://reviews.llvm.org/D53843 llvm-svn: 345641
* [x86] try to make test immune to better div optimization; NFCISanjay Patel2018-10-301-26/+25
| | | | llvm-svn: 345640
* [x86] try to make test immune to better div optimization; NFCISanjay Patel2018-10-301-20/+14
| | | | llvm-svn: 345639
* [DAGCombiner] Fix for big endian in ForwardStoreValueToDirectLoadBjorn Pettersson2018-10-301-0/+77
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: Normalize the offset for endianess before checking if the store cover the load in ForwardStoreValueToDirectLoad. Without this we missed out on some optimizations for big endian targets. If for example having a 4 bytes store followed by a 1 byte load, loading the least significant byte from the store, the STCoversLD check would fail (see @test4 in test/CodeGen/AArch64/load-store-forwarding.ll). This patch also fixes a problem seen in an out-of-tree target. The target has i40 as a legal type, it is big endian, and the StoreSize for i40 is 48 bits. So when normalizing the offset for endianess we need to take the StoreSize into account (assuming that padding added when storing into a larger StoreSize always is added at the most significant end). Reviewers: niravd Reviewed By: niravd Subscribers: javed.absar, kristof.beyls, llvm-commits, uabelho Differential Revision: https://reviews.llvm.org/D53776 llvm-svn: 345636
* [AArch64] [Windows] SEH opcodes should be scheduling boundaries.Eli Friedman2018-10-307-7/+7
| | | | | | | | | | | | | | Prevents the post-RA scheduler from modifying the prologue sequences emitting by frame lowering. This is roughly similar to what we do for other targets: TargetInstrInfo::isSchedulingBoundary checks isPosition(), which checks for CFI_INSTRUCTION. isSEHInstruction is taken from D50288; it'll land with whatever patch lands first. Differential Revision: https://reviews.llvm.org/D53851 llvm-svn: 345634
* [AArch64] Create proper memoperand for multi-vector storesDavid Greene2018-10-301-0/+82
| | | | | | | | | | | | Re-apply r345315 with testcase fixes. Include all of the store's source vector operands when creating the MachineMemOperand. Previously, we were missing the first operand, making the store size seem smaller than it really is. Differential Revision: https://reviews.llvm.org/D52816 llvm-svn: 345631
* [X86] In lowerVectorShuffleAsBroadcast, make peeking through CONCAT_VECTORS ↵Craig Topper2018-10-301-0/+29
| | | | | | | | | | | | work correctly if we already walked through a bitcast that changed the element size. The CONCAT_VECTORS case was using the original mask element count to determine how to adjust the broadcast index. But if we looked through a bitcast the original mask size doesn't tell us anything about the concat_vectors. This patch switchs to using the concat_vectors input element count directly instead. Differential Revision: https://reviews.llvm.org/D53823 llvm-svn: 345626
* [SchedModel] Fix for read advance cycles with implicit pseudo operands.Jonas Paulsson2018-10-3031-230/+262
| | | | | | | | | | | | | | | | | | The SchedModel allows the addition of ReadAdvances to express that certain operands of the instructions are needed at a later point than the others. RegAlloc may add pseudo operands that are not part of the instruction descriptor, and therefore cannot have any read advance entries. This meant that in some cases the desired read advance was nullified by such a pseudo operand, which still had the original latency. This patch fixes this by making sure that such pseudo operands get a zero latency during DAG construction. Review: Matthias Braun, Ulrich Weigand. https://reviews.llvm.org/D49671 llvm-svn: 345606
* [DAGCombiner] narrow vector binops when extraction is cheapSanjay Patel2018-10-3023-457/+357
| | | | | | | | | | | | | | | | | Narrowing vector binops came up in the demanded bits discussion in D52912. I don't think we're going to be able to do this transform in IR as a canonicalization because of the risk of creating unsupported widths for vector ops, but we already have a DAG TLI hook to allow what I was hoping for: isExtractSubvectorCheap(). This is currently enabled for x86, ARM, and AArch64 (although only x86 has existing regression test diffs). This is artificially limited to not look through bitcasts because there are so many test diffs already, but that's marked with a TODO and is a small follow-up. Differential Revision: https://reviews.llvm.org/D53784 llvm-svn: 345602
* [llc] Error out when -print-machineinstrs is used with an unknown passFrancis Visoiu Mistrih2018-10-301-0/+12
| | | | | | | | We used to assert instead of reporting an error. PR39494 llvm-svn: 345589
* [X86] Add extra-uses on the mask of pattern c of extract-{low,}bits.ll testsRoman Lebedev2018-10-302-609/+2087
| | | | | | | | | | | | | | | | Summary: Because of the D48768, that pattern is always unfolded into pattern d, thus we had no test coverage. Reviewers: RKSimon, craig.topper Reviewed By: craig.topper Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D53574 llvm-svn: 345583
* [SelectionDAG] Add FoldBUILD_VECTOR to simplify new BUILD_VECTOR nodesSimon Pilgrim2018-10-303-158/+12
| | | | | | | | | | Similar to FoldCONCAT_VECTORS, this patch adds FoldBUILD_VECTOR to simplify cases that can avoid the creation of the BUILD_VECTOR - if all the operands are UNDEF or if the BUILD_VECTOR simplifies to a copy. This exposed an assumption in some AMDGPU code that getBuildVector was guaranteed to be a BUILD_VECTOR node that I've tried to handle. Differential Revision: https://reviews.llvm.org/D53760 llvm-svn: 345578
* [DAGCombiner] Improve X div/rem Y fold if single bit element typeDavid Bolvansky2018-10-309-937/+58
| | | | | | | | | | | | | | Summary: Tests by @spatel, thanks Reviewers: spatel, RKSimon Reviewed By: spatel Subscribers: sdardis, atanasyan, llvm-commits, spatel Differential Revision: https://reviews.llvm.org/D52668 llvm-svn: 345575
* [LegalizeTypes] Teach PromoteIntRes_BITCAST to better handle a bitcast with ↵Craig Topper2018-10-301-9/+5
| | | | | | | | | | | | | | | | vector output type and a vector input type that needs to be widened Summary: Previously if we had a bitcast vector output type that needs promotion and a vector input type that needs widening we would just do a stack store and load to handle the conversion. We can do a little better if we can widen the bitcast to a legal vector type the same size as the widened input type. Then we can do the bitcast between this widened type and the widened input type. Afterwards we can extract_subvector back to the original output and any_extend that. Type legalization will then circle back and handle promotion of the extract_subvector and the any_extend will just be removed. This will avoid going through the stack and allows us to remove a custom version of this legalization from X86. Reviewers: efriedma, RKSimon Reviewed By: efriedma Subscribers: javed.absar, llvm-commits Differential Revision: https://reviews.llvm.org/D53229 llvm-svn: 345567
* [AArch64] Add test case for D53229. NFCCraig Topper2018-10-301-0/+31
| | | | llvm-svn: 345566
* AMDGPU: Remove custom BUILD_VECTOR combineMatt Arsenault2018-10-302-6/+33
| | | | | | | This was looping in a testcase and removing it now slightly improves a test. llvm-svn: 345560
* AMDGPU: Use scavengeRegisterBackwardsMatt Arsenault2018-10-302-44/+48
| | | | llvm-svn: 345559
* AMDGPU: Enable code object v3 by defaultKonstantin Zhuravlyov2018-10-2933-120/+120
| | | | | | Differential Revision: https://reviews.llvm.org/D53525 llvm-svn: 345542
* [MachineOutliner] Inherit target features from parent functionJessica Paquette2018-10-291-1/+11
| | | | | | | | | | | | | | | If a function has target features, it may contain instructions that aren't represented in the default set of instructions. If the outliner pulls out one of these instructions, and the function doesn't have the right attributes attached, we'll run into an LLVM error explaining that the target doesn't support the necessary feature for the instruction. This makes outlined functions inherit target features from their parents. It also updates the machine-outliner.ll test to check that we're properly inheriting target features. llvm-svn: 345535
* Relax fast register allocator related test cases; NFCMatthias Braun2018-10-2936-252/+274
| | | | | | | | | | | | | - Relex hard coded registers and stack frame sizes - Some test cleanups - Change phi-dbg.ll to match on mir output after phi elimination instead of going through the whole codegen pipeline. This is in preparation for https://reviews.llvm.org/D52010 I'm committing all the test changes upfront that work before and after independently. llvm-svn: 345532
* [WebAssembly] Lower away condition truncations for scalar selectsThomas Lively2018-10-291-1/+41
| | | | | | | | | | Reviewers: aheejin, dschuff Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D53676 llvm-svn: 345521
* [X86][SSE] getFauxShuffleMask - Fix shuffle mask adjustment for multiple ↵Simon Pilgrim2018-10-291-0/+97
| | | | | | | | inserted subvectors Part of the issue discovered in PR39483, although its not fully exposed until I reapply rL345395 (by reverting rL345451) llvm-svn: 345520
* [AMDGPU] Match v_swap_b32Stanislav Mekhanoshin2018-10-291-0/+564
| | | | | | Differential Revision: https://reviews.llvm.org/D52677 llvm-svn: 345514
* [X86] Enable the MachineVerifier by defaultFrancis Visoiu Mistrih2018-10-298-13/+21
| | | | | | | | | | | | | | | The machine verifier was disabled for x86 by default. There are now only 9 tests failing, compared to what previously was between 20 and 30. This is a good opportunity to file bugs for all the remaining issues, then explicitly disable the failing tests and enabling the machine verifier by default. This allows us to avoid adding new tests that break the verifier. PR27481 llvm-svn: 345513
* [Intrinsic] Signed and Unsigned Saturation Subtraction IntirnsicsLeonard Chan2018-10-292-0/+425
| | | | | | | | | | | | Add an intrinsic that takes 2 integers and perform saturation subtraction on them. This is a part of implementing fixed point arithmetic in clang where some of the more complex operations will be implemented as intrinsics. Differential Revision: https://reviews.llvm.org/D53783 llvm-svn: 345512
* [AArch64] Return address signing B key supportLuke Cheeseman2018-10-291-0/+23
| | | | | | | | | | | - Add support to generate AUTIBSP, PACIBSP, RETAB instructions for return address signing - The key used to sign the function is controlled by the function attribute "sign-return-address-key" Differential Revision: https://reviews.llvm.org/D51427 llvm-svn: 345511
* [X86] Remove outdated testFrancis Visoiu Mistrih2018-10-291-288/+0
| | | | | | | | | | | This test breaks the X86 MachineVerifier. It looks like the MIR part is completely useless. The original author suggests that it can be removed. Differential Revision: https://reviews.llvm.org/D53767 llvm-svn: 345501
* [ARM][NFC] Fix test inlineasm-X-allocation.llSjoerd Meijer2018-10-291-15/+14
| | | | | | Differential Revision: https://reviews.llvm.org/D53748 llvm-svn: 345491
* [X86] Force floating point values in constant pool decoding to print in ↵Craig Topper2018-10-2948-490/+490
| | | | | | | | | | scientific notation so they can't be confused with integers. When the floating point constants are whole numbers they have no decimal point so look like integers, but mean something very different in something like an 'and' instruction. Ideally we would just print a decimal point and a 0, but I couldn't see how to make APFloat::toString do that. llvm-svn: 345488
* [X86] Recognize constant splats in LowerFCOPYSIGN.Craig Topper2018-10-281-6/+4
| | | | llvm-svn: 345484
* [X86] Add test case to show failure to handle splat vectors in the constant ↵Craig Topper2018-10-281-0/+20
| | | | | | check in LowerFCOPYSIGN. llvm-svn: 345483
* [X86][NFC] sse42-schedule.ll: disable XOP for BdVer2 testsRoman Lebedev2018-10-281-3/+3
| | | | | | Else we are clearly testing the wrong instruction. llvm-svn: 345476
* [X86][NFC] sse41-schedule.ll: disable XOP for BdVer2 testsRoman Lebedev2018-10-281-3/+3
| | | | | | Else we are clearly testing the wrong instruction. llvm-svn: 345475
* [X86][NFC] sse2-schedule.ll: disable XOP for BdVer2 testsRoman Lebedev2018-10-281-13/+13
| | | | | | Else we are clearly testing the wrong instruction. llvm-svn: 345474
* [VectorLegalizer] Enable TargetLowering::expandFP_TO_UINT support.Simon Pilgrim2018-10-283-171/+144
| | | | | | | | Add vector support to TargetLowering::expandFP_TO_UINT. This exposes an issue in X86TargetLowering::LowerVSELECT which was assuming that the select mask was the same width as the LHS/RHS ops - as long as the result is a sign splat we can easily sext/trunk this. llvm-svn: 345473
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