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* [mips] MIPSR6 Compact branch aliasesSimon Dardis2016-04-125-48/+54
| | | | | | | | | | | | Summary: Alias 'jic $reg, 0' to 'jrc $reg' and 'jialc $reg, 0' to 'jalrc $reg' like binutils. Reviewers: dsanders Differential Revision: http://reviews.llvm.org/D18856 llvm-svn: 266055
* [PPC64] Mark CR0 Live if PPCInstrInfo::optimizeCompareInstr Creates a Use of CR0Chuang-Yu Cheng2016-04-121-0/+23
| | | | | | | | | | | | | | Resolve Bug 27046 (https://llvm.org/bugs/show_bug.cgi?id=27046). The PPCInstrInfo::optimizeCompareInstr function could create a new use of CR0, even if CR0 were previously dead. This patch marks CR0 live if a use of CR0 is created. Author: Tom Jablin (tjablin) Reviewers: hfinkel kbarton cycheng http://reviews.llvm.org/D18884 llvm-svn: 266040
* [PPC64] Use mfocrf in prologue when we only need to save 1 nonvolatile CR fieldChuang-Yu Cheng2016-04-122-1/+21
| | | | | | | | | | | | | | In the ELFv2 ABI, we are not required to save all CR fields. If only one nonvolatile CR field is clobbered, use mfocrf instead of mfcr to selectively save the field, because mfocrf has short latency compares to mfcr. Thanks Nemanja's invaluable hint! Reviewers: nemanjai tjablin hfinkel kbarton http://reviews.llvm.org/D17749 llvm-svn: 266038
* [AArch64] Add test cases for the repairing of physical registers.Quentin Colombet2016-04-121-0/+48
| | | | llvm-svn: 266030
* [AArch64] Add a test case for the propagation of register banks throughQuentin Colombet2016-04-121-0/+49
| | | | | | phis. llvm-svn: 266028
* [AArch64] Add a test case for the repairing of definitions.Quentin Colombet2016-04-121-0/+28
| | | | llvm-svn: 266026
* [AArch64] Test that RegBankSelect inserts the proper copies to fix theQuentin Colombet2016-04-121-0/+53
| | | | | | register bank assignments. llvm-svn: 266021
* [safestack] Add canary to unsafe stack framesEvgeniy Stepanov2016-04-111-0/+27
| | | | | | | | Add StackProtector to SafeStack. This adds limited protection against data corruption in the caller frame. Current implementation treats all stack protector levels as -fstack-protector-all. llvm-svn: 266004
* ARM: use r7 as the frame-pointer on all MachO targets.Tim Northover2016-04-113-9/+11
| | | | | | | | | | | | This is better for a few reasons: + It matches the other tooling for iOS. + It matches EABI in more cases (i.e. Thumb-mode, and in practice we don't use ARM mode). + It leads to infinitesimally smaller code (0.2%, yay!). rdar://25369506 llvm-svn: 266003
* swifterror: fix up a testing case.Manman Ren2016-04-111-5/+5
| | | | llvm-svn: 266000
* [DAGCombiner] Fold xor/and/or (bitcast(A), bitcast(B)) -> bitcast(op (A,B)) ↵Simon Pilgrim2016-04-118-2415/+297
| | | | | | | | | | | | | | anytime before LegalizeVectorOprs xor/and/or (bitcast(A), bitcast(B)) -> bitcast(op (A,B)) was only being combined at the AfterLegalizeTypes stage, this patch permits the combine to occur anytime before then as well. The main aim with this to improve the ability to recognise bitmasks that can be converted to shuffles. I had to modify a number of AVX512 mask tests as the basic bitcast to/from scalar pattern was being stripped out, preventing testing of the mmask bitops. By replacing the bitcasts with loads we can get almost the same result. Differential Revision: http://reviews.llvm.org/D18944 llvm-svn: 265998
* Swift Calling Convention: swifterror target support.Manman Ren2016-04-113-0/+1125
| | | | | | Differential Revision: http://reviews.llvm.org/D18716 llvm-svn: 265997
* Revert "AMDGPU/SI: Do not generate s_waitcnt after ds_permute/ds_bpermute"Tom Stellard2016-04-112-50/+4
| | | | | | | | This reverts commit r263720. Just confirmed that s_waitcnt is required after ds_permute/ds_bpermute. llvm-svn: 265992
* More upgrading of old- and very-old-style debug info in testcases.Adrian Prantl2016-04-116-4/+8
| | | | llvm-svn: 265953
* [mips] Make Static a default relocation model for MIPS codegenPetar Jovanovic2016-04-1173-328/+333
| | | | | | | | | | | | This change follows up defaults for GCC and Clang, so LLVM does not differ from them. While number of the test files are touched with this change, they all keep the old (expected) behaviour with the explicit option: "-relocation-model=pic" The tests that have not been touched are insensitive to relocation model. Differential Revision: http://reviews.llvm.org/D17995 llvm-svn: 265949
* [SystemZ] Support conditional indirect sibling calls via BCRUlrich Weigand2016-04-111-0/+467
| | | | | | | | | | | | | | | This adds a conditional variant of CallBR instruction, CallBCR. Also, it can be fused with integer comparisons, resulting in one of the new C*BCall instructions. In addition to CallBRCL limitations, this has another one: it won't trigger if the function to call isn't already in %r1 - see f22 in the test for an example (it's also why the loads in tests are volatile). Author: koriakin Differential Revision: http://reviews.llvm.org/D18928 llvm-svn: 265933
* [X86] Added extra widening tests for and/xor/or bit operationsSimon Pilgrim2016-04-111-0/+1315
| | | | | | | | Add tests for bitcasting an illegal vector to/from a legal scalar Additional tests requested for D18944 llvm-svn: 265930
* [X86] Added extra widening tests for and/xor/or bit operationsSimon Pilgrim2016-04-111-0/+733
| | | | | | To make sure we're dealing with both cases of legal/illegal number of vector elements and legal/illegal vector element types llvm-svn: 265929
* [X86] Regenerated sdglue test checksSimon Pilgrim2016-04-111-12/+24
| | | | llvm-svn: 265927
* [X86] Added widening tests for and/xor/or bit operationsSimon Pilgrim2016-04-111-0/+663
| | | | | | Part of additional tests requested for D18944 llvm-svn: 265925
* [X86][AVX512] Add vector integer division by constant testsSimon Pilgrim2016-04-102-0/+4428
| | | | | | Added sdiv/srem and udiv/urem tests cases for 512 bit vectors. llvm-svn: 265903
* [X86][AVX512BW] Add support for v64i8 multipliesSimon Pilgrim2016-04-101-592/+21
| | | | | | | | | | Extend the existing lowering of vXi8 multiplies to support v64i8 on avx512bw targets. I added the Lower512IntArith helper function to help with this - not sure how often this could be used in the future, but it seemed better than putting all that logic inside LowerMUL. Differential Revision: http://reviews.llvm.org/D18937 llvm-svn: 265902
* [X86][AVX512] Regenerated mask op testsSimon Pilgrim2016-04-102-39/+67
| | | | llvm-svn: 265898
* [CodeGen] Don't assume that fixed stack objects are aligned in a ↵Charles Davis2016-04-091-0/+28
| | | | | | | | | | | | | | | | | | | | stack-realigned function. Summary: After we make the adjustment, we can assume that for local allocas, but not for stack parameters, the return address, or any other fixed stack object (which has a negative offset and therefore lies prior to the adjusted SP). Fixes PR26662. Reviewers: hfinkel, qcolombet, rnk Subscribers: rnk, llvm-commits Differential Revision: http://reviews.llvm.org/D18471 llvm-svn: 265886
* [x86] use BMI 'andn' for logic + compare ops Sanjay Patel2016-04-091-6/+4
| | | | | | | | | | With BMI, we can use 'andn' to save an instruction when the result is only used in a compare. This is related to one of the potential sequences to check 'isfinite' in: https://llvm.org/bugs/show_bug.cgi?id=27164 Differential Revision: http://reviews.llvm.org/D18910 llvm-svn: 265875
* [X86][XOP] Support for VPPERM 2-input shuffle mask decodingSimon Pilgrim2016-04-091-4/+4
| | | | | | | | | | This patch adds support for decoding XOP VPPERM instruction when it represents a basic shuffle. The mask decoding required the existing MCInstrLowering code to be updated to support binary shuffles - the implementation now matches what is done in X86InstrComments.cpp. Differential Revision: http://reviews.llvm.org/D18441 llvm-svn: 265874
* [x86] show missed opportunities to use andnSanjay Patel2016-04-081-0/+45
| | | | llvm-svn: 265850
* [x86] regenerate checks for BMI testsSanjay Patel2016-04-081-149/+296
| | | | llvm-svn: 265841
* Add trailing colons to labels in a test.James Y Knight2016-04-081-12/+12
| | | | | | | This will avoid matching on the FILENAME if it happened to contain, say, "f4" anywhere in the file path. llvm-svn: 265837
* Fix Load Control Dependence in MemCpy GenerationNirav Dave2016-04-081-8/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In Memcpy lowering we had missed a dependence from the load of the operation to successor operations. This causes us to potentially construct an in initial DAG with a memory dependence not fully represented in the chain sub-DAG but rather require looking at the entire DAG breaking alias analysis by allowing incorrect repositioning of memory operations. To work around this, r200033 changed DAGCombiner::GatherAllAliases to be conservative if any possible issues to happen. Unfortunately this check forbade many non-problematic situations as well. For example, it's common for incoming argument lowering to add a non-aliasing load hanging off of EntryNode. Then, if GatherAllAliases visited EntryNode, it would find that other (unvisited) use of the EntryNode chain, and just give up entirely. Furthermore, the check was incomplete: it would not actually detect all such potentially problematic DAG constructions, because GatherAllAliases did not guarantee to visit all chain nodes going up to the root EntryNode. This is in general fine -- giving up early will just miss a potential optimization, not generate incorrect results. But, for this non-chain dependency detection code, it's possible that you could have a load attached to a higher-up chain node than any which were visited. If that load aliases your store, but the only dependency is through the value operand of a non-aliasing store, it would've been missed by this code, and potentially reordered. With the dependence added, this check can be removed and Alias Analysis can be much more aggressive. This fixes code quality regression in the Consecutive Store Merge cleanup (D14834). Test Change: ppc64-align-long-double.ll now may see multiple serializations of its stores Differential Revision: http://reviews.llvm.org/D18062 llvm-svn: 265836
* [X86] Fix PR23155 by turning on X86FixupBWInsts by default.Kevin B. Smith2016-04-083-4/+4
| | | | | | Differential Revision: http://reviews.llvm.org/D18866 llvm-svn: 265830
* Revert r265817Colin LeMahieu2016-04-088-13/+13
| | | | | | lld tests need to be addressed. llvm-svn: 265822
* [llvm-objdump] Printing hex instead of dec by defaultColin LeMahieu2016-04-088-13/+13
| | | | | | Differential Revision: http://reviews.llvm.org/D18770 llvm-svn: 265817
* [SystemZ] Support conditional sibling calls via BRCLUlrich Weigand2016-04-081-0/+369
| | | | | | | | | | | | This adds a conditional variant of CallJG instruction, CallBRCL. It can be used for conditional sibling calls. Unfortunately, due to IfCvt limitations, it only really works well for functions without arguments. Author: koriakin Differential Revision: http://reviews.llvm.org/D18864 llvm-svn: 265814
* [AArch64] Add a test case for the default mapping of RegBankSelect.Quentin Colombet2016-04-081-0/+49
| | | | llvm-svn: 265811
* [MIR] Teach the parser how to deal with register banks.Quentin Colombet2016-04-081-1/+1
| | | | llvm-svn: 265802
* [ARM] Enable SMLAW[B|T] and SMLUW[B|T] instruction selectionSam Parker2016-04-082-26/+105
| | | | | | | | | | Added ISelDAGToDAG functions to enable selection of the smlawb, smlawt, smulwb and smulwt instructions for the ARM backend. Also updated the smul CodeGen test and removed the smulw one. Differential Revision: http://reviews.llvm.org/D18892 llvm-svn: 265793
* Revert r265547 "Recommit r265309 after fixed an invalid memory reference bug ↵Hans Wennborg2016-04-085-199/+518
| | | | | | | | | | | | | happened" It caused PR27275: "ARM: Bad machine code: Using an undefined physical register" Also reverting the following commits that were landed on top: r265610 "Fix the compare-clang diff error introduced by r265547." r265639 "Fix the sanitizer bootstrap error in r265547." r265657 "InlineSpiller.cpp: Escap \@ in r265547. [-Wdocumentation]" llvm-svn: 265790
* [X86][SSE] Added 32-bit tests for vector lzcnt/tzcnt testsSimon Pilgrim2016-04-082-0/+607
| | | | | | v2i64 tests are particularly bad on 32-bit targets. llvm-svn: 265789
* CXX_FAST_TLS calling convention: performance improvement for PPC64Chuang-Yu Cheng2016-04-081-0/+43
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This is the same change on PPC64 as r255821 on AArch64. I have even borrowed his commit message. The access function has a short entry and a short exit, the initialization block is only run the first time. To improve the performance, we want to have a short frame at the entry and exit. We explicitly handle most of the CSRs via copies. Only the CSRs that are not handled via copies will be in CSR_SaveList. Frame lowering and prologue/epilogue insertion will generate a short frame in the entry and exit according to CSR_SaveList. The majority of the CSRs will be handled by register allcoator. Register allocator will try to spill and reload them in the initialization block. We add CSRsViaCopy, it will be explicitly handled during lowering. 1> we first set FunctionLoweringInfo->SplitCSR if conditions are met (the target supports it for the given machine function and the function has only return exits). We also call TLI->initializeSplitCSR to perform initialization. 2> we call TLI->insertCopiesSplitCSR to insert copies from CSRsViaCopy to virtual registers at beginning of the entry block and copies from virtual registers to CSRsViaCopy at beginning of the exit blocks. 3> we also need to make sure the explicit copies will not be eliminated. Author: Tom Jablin (tjablin) Reviewers: hfinkel kbarton cycheng http://reviews.llvm.org/D17533 llvm-svn: 265781
* [mips][microMIPS] Add CodeGen support for ADD, ADDIU*, ADDU* and DADD* ↵Zlatko Buljan2016-04-081-8/+317
| | | | | | | | instructions Differential Revision: http://reviews.llvm.org/D16454 llvm-svn: 265772
* [IFUNC] Fix ifunc-asm.ll testDmitry Polukhin2016-04-081-0/+15
| | | | | | | It seems that llc cannot be called used in assembler tests so test that checks asm for particular target needs to be moved to codegen. llvm-svn: 265770
* Do not select EhPad BB in MachineBlockPlacement when there is regular BB to ↵Amaury Sechet2016-04-075-63/+104
| | | | | | | | | | | | | | | | | schedule Summary: EHPad BB are not entered the classic way and therefor do not need to be placed after their predecessors. This patch make sure EHPad BB are not chosen amongst successors to form chains, and are selected as last resort when selecting the best candidate. EHPad are scheduled in reverse probability order in order to have them flow into each others naturally. Reviewers: chandlerc, majnemer, rafael, MatzeB, escha, silvas Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D17625 llvm-svn: 265726
* AMDGPU/SI: Implement atomic load/store for i32 and i64Jan Vesely2016-04-071-0/+178
| | | | | | | | | | Standard load/store instructions with GLC bit set. Reviewers: tstellardAMD, arsenm Differential Revision: http://reviews.llvm.org/D18760 llvm-svn: 265709
* AMDGPU/SI: Add latency for export instructionsTom Stellard2016-04-071-5/+4
| | | | | | | | | | Reviewers: arsenm, nhaehnle Subscribers: nhaehnle, arsenm, llvm-commits Differential Revision: http://reviews.llvm.org/D18599 llvm-svn: 265708
* [X86][SSE] Added bitmask pattern shuffle testsSimon Pilgrim2016-04-072-0/+195
| | | | | | Based on OR(AND(MASK,V0),AND(~MASK,V1)) style patterns llvm-svn: 265697
* [X86]: Fix for PR27251.Kevin B. Smith2016-04-071-2/+4
| | | | | | Differential Revision: http://reviews.llvm.org/D18850 llvm-svn: 265690
* [SystemZ] Implement conditional returnsUlrich Weigand2016-04-0773-729/+742
| | | | | | | | | | | | | | | | | | Return is now considered a predicable instruction, and is converted to a newly-added CondReturn (which maps to BCR to %r14) instruction by the if conversion pass. Also, fused compare-and-branch transform knows about conditional returns, emitting the proper fused instructions for them. This transform triggers on a *lot* of tests, hence the huge diffstat. The changes are mostly jX to br %r14 -> bXr %r14. Author: koriakin Differential Revision: http://reviews.llvm.org/D17339 llvm-svn: 265689
* [PPC] Enable transformations in PPCPassConfig::addIRPasses at O2Ehsan Amiri2016-04-0729-345/+171
| | | | | | | | | | | | | | http://reviews.llvm.org/D18562 A large number of testcases has been modified so they pass after this test. One testcase is deleted, because I realized even after undoing the original change that was committed with this testcase, the testcase still passes. So I removed it. The change to one other testcase (test/CodeGen/PowerPC/pr25802.ll) is an arbitrary change to keep it passing. Given the original intention of the testcase, and the fact that fixing it will require some time to change the testcase, we concluded that this quick change will be enough. llvm-svn: 265683
* [X86][SSE] Add support for VZEXT constant foldingSimon Pilgrim2016-04-073-6/+3
| | | | llvm-svn: 265646
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