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* Check and allow floating point registers to select the size of theEric Christopher2013-01-311-0/+42
| | | | | | | register for inline asm. This conforms to how gcc allows for effective casting of inputs into gprs (fprs is already handled). llvm-svn: 174008
* Replace some more greps with FileChecks in testsEli Bendersky2013-01-313-22/+30
| | | | llvm-svn: 174006
* Rewrite this test properly with a FileCheck instead of grepsEli Bendersky2013-01-311-8/+10
| | | | llvm-svn: 173997
* PPC QPX requires a 32-byte aligned stackHal Finkel2013-01-301-0/+23
| | | | | | | On systems which support the QPX vector instructions, the stack must be 32-byte aligned. llvm-svn: 173993
* Forgot the test case before.Evan Cheng2013-01-301-0/+40
| | | | llvm-svn: 173988
* Add definitions for the PPC a2q core marked as having QPX availableHal Finkel2013-01-301-0/+10
| | | | | | | | This is the first commit of a large series which will add support for the QPX vector instruction set to the PowerPC backend. This instruction set is used on the IBM Blue Gene/Q supercomputers. llvm-svn: 173973
* Add a special ARM trap encoding for NaCl.Eli Bendersky2013-01-301-0/+28
| | | | | | | | More details in this thread: http://lists.cs.uiuc.edu/pipermail/llvm-commits/Week-of-Mon-20130128/163783.html Patch by JF Bastien llvm-svn: 173943
* Add missing header and test cases for r173939.Logan Chien2013-01-304-0/+211
| | | | llvm-svn: 173941
* [mips] Test case for r173862.Akira Hatanaka2013-01-302-0/+164
| | | | | | Patch by Sasa Stankovic. llvm-svn: 173863
* Fix 64-bit atomic operations in Thumb mode.Tim Northover2013-01-291-0/+147
| | | | | | | | The ARM and Thumb variants of LDREXD and STREXD have different constraints and take different operands. Previously the code expanding atomic operations didn't take this into account and asserted in Thumb mode. llvm-svn: 173780
* This patch addresses bug 15031.Bill Schmidt2013-01-281-0/+370
| | | | | | | | | | | | | | | | | | | | | | The common code in the post-RA scheduler to break anti-dependencies on the critical path contained a flaw. In the reported case, an anti-dependency between the overlapping registers %X4 and %R4 exists: %X29<def> = OR8 %X4, %X4 %R4<def>, %X3<def,dead,tied3> = LBZU 1, %X3<kill,tied1> The unpatched code breaks the dependency by replacing %R4 and its uses with %R3, the first register on the available list. However, %R3 and %X3 overlap, so this creates two overlapping definitions on the same instruction. The fix is straightforward, preventing selection of a register that overlaps any other defined register on the same instruction. The test case is reduced from the bug report, and verifies that we no longer produce "lbzu 3, 1(3)" when breaking this anti-dependency. llvm-svn: 173706
* When the legalizer is splitting vector shifts, the result may not have the ↵Benjamin Kramer2013-01-271-0/+11
| | | | | | | | | | | | | | | right shift amount type. Fix that by adding a cast to the shift expander. This came up with vector shifts on sse-less X86 CPUs. <2 x i64> = shl <2 x i64> <2 x i64> -> i64,i64 = shl i64 i64; shl i64 i64 -> i32,i32,i32,i32 = shl_parts i32 i32 i64; shl_parts i32 i32 i64 Now we cast the last two i64s to the right type. Fixes the crash in PR14668. llvm-svn: 173615
* X86: Do splat promotion later, so the optimizer can chew on it first.Benjamin Kramer2013-01-262-17/+7
| | | | | | | | | | | | This catches many cases where we can emit a more efficient shuffle for a specific mask or when the mask contains undefs. Once the splat is lowered to unpacks we can't do that anymore. There is a possibility of moving the promotion after pshufb matching, but I'm not sure if pshufb with a mask loaded from memory is faster than 3 shuffles, so I avoided that for now. llvm-svn: 173569
* FileCheckize and merge some tests.Benjamin Kramer2013-01-264-127/+227
| | | | llvm-svn: 173568
* FileCheck-ify some grep testsReid Kleckner2013-01-251-2/+2
| | | | | | | | These tests in particular try to use escaped square brackets as an argument to grep, which is failing for me with native win32 python. It appears the backslash is being lost near the CreateProcess*() call. llvm-svn: 173506
* In this patch, we teach X86_64TargetMachine that it has a ILP32Eli Bendersky2013-01-252-4/+43
| | | | | | | | | | | | | | | | | | | | | (defined by the x32 ABI) mode, in which case its pointers are 32-bits in size. This knowledge is also added to X86RegisterInfo that now returns the appropriate registers in getPointerRegClass. There are many outcomes to this change. In order to keep the patches separate and manageable, we start by focusing on some simple testable cases. The patch adds a test with passing a pointer to a function - focusing on the difference between the two data models for x86-64. Another test is added for handling of 'sret' arguments (and functionality is added in X86ISelLowering to make it work). A note on naming: the "x32 ABI" document refers to the AMD64 architecture (in LLVM it's distinguished by being is64Bits() in the x86 subtarget) with two variations: the LP64 (default) data model, and the ILP32 data model. This patch adds predicates to the subtarget which are consistent with this naming scheme. llvm-svn: 173503
* Now that llvm-dwarfdump supports flags to specify which DWARF section to dump,Eli Bendersky2013-01-251-1/+1
| | | | | | | use them in tests that run llvm-dwarfdump. This is in order to make tests as specific as possible. llvm-svn: 173498
* Fixed the condition codes for the atomic64 min/umin code generation on ARM. ↵Silviu Baranga2013-01-251-2/+2
| | | | | | If the sutraction of the higher 32 bit parts gives a 0 result, we need to do the store operation. llvm-svn: 173437
* MIsched: Improve the interface to SchedDFS analysis (subtrees).Andrew Trick2013-01-251-3/+0
| | | | | | | Allow the strategy to select SchedDFS. Allow the results of SchedDFS to affect initialization of the scheduler state. llvm-svn: 173425
* MISched: Add SchedDFSResult to ScheduleDAGMI to formalize theAndrew Trick2013-01-251-0/+3
| | | | | | interface and allow other strategies to select it. llvm-svn: 173413
* [mips] Set flag neverHasSideEffects flag on some of the floating point ↵Akira Hatanaka2013-01-251-0/+13
| | | | | | instructions. llvm-svn: 173401
* The next phase of Mips16 hard float implementation.Reed Kotler2013-01-241-0/+256
| | | | | | | | | | | | | | | | Allow Mips16 routines to call Mips32 routines that have abi requirements that either arguments or return values are passed in floating point registers. This handles only the pic case. We have not done non pic for Mips16 yet in any form. The libm functions are Mips32, so with this addition we have a complete Mips16 hard float implementation. We still are not able to complete mix Mip16 and Mips32 with hard float. That will be the next phase which will have several steps. For Mips32 to freely call Mips16 some stub functions must be created. llvm-svn: 173320
* Add the heuristic to differentiate SSPStrong from SSPRequired.Bill Wendling2013-01-231-12/+2518
| | | | | | | | | | | | | | | | | | The requirements of the strong heuristic are: * A Protector is required for functions which contain an array, regardless of type or length. * A Protector is required for functions which contain a structure/union which contains an array, regardless of type or length. Note, there is no limit to the depth of nesting. * A protector is required when the address of a local variable (i.e., stack based variable) is exposed. (E.g., such as through a local whose address is taken as part of the RHS of an assignment or a local whose address is taken as part of a function argument.) llvm-svn: 173231
* Add the IR attribute 'sspstrong'.Bill Wendling2013-01-231-21/+628
| | | | | | | | | | | | | | | | | | | | | SSPStrong applies a heuristic to insert stack protectors in these situations: * A Protector is required for functions which contain an array, regardless of type or length. * A Protector is required for functions which contain a structure/union which contains an array, regardless of type or length. Note, there is no limit to the depth of nesting. * A protector is required when the address of a local variable (i.e., stack based variable) is exposed. (E.g., such as through a local whose address is taken as part of the RHS of an assignment or a local whose address is taken as part of a function argument.) This patch implements the SSPString attribute to be equivalent to SSPRequired. This will change in a subsequent patch. llvm-svn: 173230
* Fix an issue of pseudo atomic instruction DAG scheduleMichael Liao2013-01-221-0/+110
| | | | | | | | | | - Add list of physical registers clobbered in pseudo atomic insts Physical registers are clobbered when pseudo atomic instructions are expanded. Add them in clobber list to prevent DAG scheduler to mis-schedule them after these insns are declared side-effect free. - Add test case from Michael Kuperstein <michael.m.kuperstein@intel.com> llvm-svn: 173200
* [mips] Implement MipsRegisterInfo::getRegPressureLimit.Akira Hatanaka2013-01-223-7/+7
| | | | llvm-svn: 173197
* llvm/test/CodeGen/X86/win_ftol2.ll: Add -cpu=generic to appease valgrind.NAKAMURA Takumi2013-01-201-1/+1
| | | | | | | On valgrind the processor is reported; Host CPU: athlon-fx llvm-svn: 172983
* Revert 172708.Nadav Rotem2013-01-202-68/+0
| | | | | | | | | The optimization handles esoteric cases but adds a lot of complexity both to the X86 backend and to other backends. This optimization disables an important canonicalization of chains of SEXT nodes and makes SEXT and ZEXT asymmetrical. Disabling the canonicalization of consecutive SEXT nodes into a single node disables other DAG optimizations that assume that there is only one SEXT node. The AVX mask optimizations is one example. Additionally this optimization does not update the cost model. llvm-svn: 172968
* On Sandybridge split unaligned 256bit stores into two xmm-sized stores. Nadav Rotem2013-01-198-27/+38
| | | | llvm-svn: 172894
* Remove some register allocation order dependencies.Jakob Stoklund Olesen2013-01-194-12/+12
| | | | llvm-svn: 172874
* On Sandybridge loading unaligned 256bits using two XMM loads (vmovups and ↵Nadav Rotem2013-01-182-1/+22
| | | | | | vinsertf128) is faster than using a single vmovups instruction. llvm-svn: 172868
* llvm/test/CodeGen/X86/Atomics-64.ll: Tweak for 2nd RUN not to overwrite %t. ↵NAKAMURA Takumi2013-01-181-2/+2
| | | | | | | | It sometimes causes spurious failure on lit win32. Feel free to prune or suppress each output. llvm-svn: 172823
* Restore reverted test case, this time with REQUIRES: assertsBill Schmidt2013-01-171-0/+19
| | | | llvm-svn: 172747
* Remove bad test caseBill Schmidt2013-01-171-18/+0
| | | | llvm-svn: 172746
* This patch fixes PR13626 by providing i128 support in the returnBill Schmidt2013-01-171-0/+18
| | | | | | | calling convention. 128-bit integers are now properly returned in GPR3 and GPR4 on PowerPC. llvm-svn: 172745
* Add indexed load/store instructions for offset validation check.Jyotsna Verma2013-01-171-0/+36
| | | | | | This patch fixes bug 14902 - http://llvm.org/bugs/show_bug.cgi?id=14902 llvm-svn: 172737
* This patch fixes the PPC calling convention to handle returns ofBill Schmidt2013-01-171-0/+55
| | | | | | | | | _Complex float and _Complex long double, by simply increasing the number of floating point registers available for return values. The test case verifies that the correct registers are loaded. llvm-svn: 172733
* Optimization for the following SIGN_EXTEND pairs:Elena Demikhovsky2013-01-172-0/+80
| | | | | | | | | | | | v8i8 -> v8i64, v8i8 -> v8i32, v4i8 -> v4i64, v4i16 -> v4i64 for AVX and AVX2. Bug 14865. llvm-svn: 172708
* This patch addresses an incorrect transformation in the DAG combiner.Bill Schmidt2013-01-141-0/+34
| | | | | | | | | | | | | | | | | | | | | | The included test case is derived from one of the GCC compatibility tests. The problem arises after the selection DAG has been converted to type-legalized form. The combiner first sees a 64-bit load that can be converted into a pre-increment form. The original load feeds into a SRL that isolates the upper 32 bits of the loaded doubleword. This looks like an opportunity for DAGCombiner::ReduceLoadWidth() to replace the 64-bit load with a 32-bit load. However, this transformation is not valid, as the replacement load is not a pre-increment load. The pre-increment load produces an extra result, which feeds a subsequent add instruction. The replacement load only has one result value, and this value is propagated to all uses of the pre- increment load, including the add. Because the add is looking for the second result value as its operand, it ends up attempting to add a constant to a token chain, resulting in a crash. So the patch simply disables this transformation for any load with more than two result values. llvm-svn: 172480
* X86: Add patterns for X86ISD::VSEXT in registers.Benjamin Kramer2013-01-131-0/+176
| | | | | | | Those can occur when something between the sextload and the store is on the same chain and blocks isel. Fixes PR14887. llvm-svn: 172353
* When lowering an inreg sext first shift left, then right arithmetically.Benjamin Kramer2013-01-121-3/+3
| | | | | | | Shifting right two times will only yield zero. Should fix SingleSource/UnitTests/SignlessTypes/factor. llvm-svn: 172322
* PPC: Implement efficient lowering of sign_extend_inreg.Nadav Rotem2013-01-111-87/+9
| | | | llvm-svn: 172269
* Update patch for the pad short functions pass for Intel Atom (only).Preston Gurd2013-01-111-0/+25
| | | | | | | | | Adds a check for -Oz, changes the code to not re-visit BBs, and skips over DBG_VALUE instrs. Patch by Andy Zhang. llvm-svn: 172258
* For inline asm:Eric Christopher2013-01-111-0/+21
| | | | | | | | | | | - recognize string "{memory}" in the MI generation - mark as mayload/maystore when there's a memory clobber constraint. PR14859. Patch by Krzysztof Parzyszek llvm-svn: 172228
* Simplify writing floating types to assembly.Tim Northover2013-01-114-18/+74
| | | | | | | This removes previous special cases for each floating-point type in favour of a shared codepath. llvm-svn: 172189
* llvm/test/CodeGen/X86/ms-inline-asm.ll: Fixup; Globals doesn't have leading ↵NAKAMURA Takumi2013-01-101-2/+2
| | | | | | underscore in symbol on linux. llvm-svn: 172139
* PR14896: Handle memcpy from constant string where the memcpy size is larger ↵Evan Cheng2013-01-101-0/+13
| | | | | | than the string size. llvm-svn: 172124
* [ms-inline asm] Add support for calling functions from inline assembly.Chad Rosier2013-01-101-0/+18
| | | | | | Part of rdar://12991541 llvm-svn: 172121
* Stack Alignment: throw error if we can't satisfy the minimal alignmentManman Ren2013-01-102-1/+20
| | | | | | | | | | | | | | | | | | requirement when creating stack objects in MachineFrameInfo. Add CreateStackObjectWithMinAlign to throw error when the minimal alignment can't be achieved and to clamp the alignment when the preferred alignment can't be achieved. Same is true for CreateVariableSizedObject. Will not emit error in CreateSpillStackObject or CreateStackObject. As long as callers of CreateStackObject do not assume the object will be aligned at the requested alignment, we should not have miscompile since later optimizations which look at the object's alignment will have the correct information. rdar://12713765 llvm-svn: 172027
* Fix a DAG combine bug visitBRCOND() is transforming br(xor(x, y)) to br(x != y).Evan Cheng2013-01-091-0/+41
| | | | | | | | | It cahced XOR's operands before calling visitXOR() but failed to update the operands when visitXOR changed the XOR node. rdar://12968664 llvm-svn: 171999
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