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* Take care of long short branch immediate instructions for mips16 inReed Kotler2013-11-132-0/+59
| | | | | | constant islands. llvm-svn: 194630
* R600/SI: Add support for private address space load/storeTom Stellard2013-11-134-20/+27
| | | | | | | Private address space is emulated using the register file with MOVRELS and MOVRELD instructions. llvm-svn: 194626
* R600/SI: Prefer SALU instructions for bit shift operationsTom Stellard2013-11-138-109/+128
| | | | | | | | | | | | | | All shift operations will be selected as SALU instructions and then if necessary lowered to VALU instructions in the SIFixSGPRCopies pass. This allows us to do more operations on the SALU which will improve performance and is also required for implementing private memory using indirect addressing, since the private memory pointers must stay in the scalar registers. This patch includes some fixes from Matt Arsenault. llvm-svn: 194625
* [AArch64] Add support for legacy AArch32 NEON scalar shift by immediateChad Rosier2013-11-131-18/+18
| | | | | | | | instructions. This patch does not include the shift right and accumulate instructions. A number of non-overloaded intrinsics have been remove in favor of their overloaded counterparts. llvm-svn: 194598
* Enable generating legacy IT block for AArch32Weiming Zhao2013-11-139-2/+15
| | | | | | | | | | | | | | By default, the behavior of IT block generation will be determinated dynamically base on the arch (armv8 vs armv7). This patch adds backend options: -arm-restrict-it and -arm-no-restrict-it. The former one restricts the generation of IT blocks (the same behavior as thumbv8) for both arches. The later one allows the generation of legacy IT block (the same behavior as ARMv7 Thumb2) for both arches. Clang will support -mrestrict-it and -mno-restrict-it, which is compatible with GCC. llvm-svn: 194592
* Remove AllowQuotesInName and friends from MCAsmInfo.Rafael Espindola2013-11-132-14/+14
| | | | | | | | | | | Accepting quotes is a property of an assembler, not of an object file. For example, ELF can support any names for sections and symbols, but the gnu assembler only accepts quotes in some contexts and llvm-mc in a few more. LLVM should not produce different symbols based on a guess about which assembler will be reading the code it is printing. llvm-svn: 194575
* XCore target: implement exception handlingRobert Lytton2013-11-132-8/+137
| | | | llvm-svn: 194564
* Allow the code which returns the length for inline assembler to knowReed Kotler2013-11-131-0/+29
| | | | | | | | | specifically about the .space directive. This allows us to force large blocks of code to appear in test cases for things like constant islands without having to make giant test cases to force things like long branches to take effect. llvm-svn: 194555
* Add a test case to verify that misusing anyregcc crashes as expected.Andrew Trick2013-11-131-0/+17
| | | | llvm-svn: 194553
* R600: Fix selection failure on EXTLOADMatt Arsenault2013-11-131-0/+51
| | | | llvm-svn: 194547
* SelectionDAG: Teach the legalizer to split SETCC if VSELECT needs splitting too.Juergen Ributzka2013-11-131-0/+42
| | | | | | | | | | | | | | | | | | | | | | This patch reapplies r193676 with an additional fix for the Hexagon backend. The SystemZ backend has already been fixed by r194148. The Type Legalizer recognizes that VSELECT needs to be split, because the type is to wide for the given target. The same does not always apply to SETCC, because less space is required to encode the result of a comparison. As a result VSELECT is split and SETCC is unrolled into scalar comparisons. This commit fixes the issue by checking for VSELECT-SETCC patterns in the DAG Combiner. If a matching pattern is found, then the result mask of SETCC is promoted to the expected vector mask type for the given target. Now the type legalizer will split both VSELECT and SETCC. This allows the following X86 DAG Combine code to sucessfully detect the MIN/MAX pattern. This fixes PR16695, PR17002, and <rdar://problem/14594431>. Reviewed by Nadav llvm-svn: 194542
* Cleanup the stackmap operand folding code and fix a corner case.Andrew Trick2013-11-121-1/+21
| | | | | | | I still don't know how to refer to the fixed operands symbolically. I plan to look into it. llvm-svn: 194529
* [mips] Fix a bug in function CC_MipsO32_FP64. The second double precisionAkira Hatanaka2013-11-121-6/+6
| | | | | | | argument was not being passed in $f14. llvm-svn: 194522
* [mips] Run test case with command line option -mattr=+fp64.Akira Hatanaka2013-11-121-16/+39
| | | | llvm-svn: 194519
* [mips] Fix and re-enable a test case that has been disabled for a long time.Akira Hatanaka2013-11-121-99/+120
| | | | llvm-svn: 194510
* Simplify operand folding when rematerializing a load.Andrew Trick2013-11-121-11/+6
| | | | | | | | | | | | We already know how to fold a reload from a frameindex without analyzing the load instruction. Generalize this to handle any frameindex load. This streamlines the logic for rematerializing loads from stack arguments. As a side effect, it allows stackmaps to record a stack argument location without spilling it. Verified no effect on codegen for llvm test-suite. llvm-svn: 194497
* [mips][msa] Enable inlinse assembly for MSA.Daniel Sanders2013-11-121-0/+34
| | | | | | | | | | | | | | Like GCC, this re-uses the 'f' constraint and a new 'w' print-modifier: asm ("ldi.w %w0, 1", "=f"(result)); Unlike GCC, the 'w' print-modifer is not _required_ to produce the intended output. This is a consequence of differences in the internal handling of the registers in each compiler. To be source-compatible between the compilers, users must use the 'w' print-modifier. MSA registers (including control registers) are supported in clobber lists. llvm-svn: 194476
* [mips][msa] Added support for matching bclr, and bclri from normal IR (i.e. ↵Daniel Sanders2013-11-122-1/+139
| | | | | | not intrinsics) llvm-svn: 194471
* [ARM] Add support for FP_HP_extension build attributeBradley Smith2013-11-122-6/+24
| | | | llvm-svn: 194470
* [mips][msa] Added support for matching bset, bseti, bneg, and bnegi from ↵Daniel Sanders2013-11-121-0/+248
| | | | | | normal IR (i.e. not intrinsics) llvm-svn: 194469
* [mips][msa] Change constant used in ori tests to avoid conflict with bseti ↵Daniel Sanders2013-11-121-16/+16
| | | | | | | | | | | | (also xori to avoid bnegi) Upcoming commit(s) are going to add support for bseti and bnegi. This would cause some existing tests to (correctly) change behaviour and emit a different instruction. This patch prevents this by changing the constant used in ori and xori tests so that they will not be matchable by the bseti and bnegi patterns when these instructions are matchable from normal IR. llvm-svn: 194467
* XCore target: fix bug in aligning 'byval i8*' on the stackRobert Lytton2013-11-121-0/+15
| | | | llvm-svn: 194466
* XCore target test for hidden declarationRobert Lytton2013-11-121-1/+5
| | | | llvm-svn: 194465
* Add XCore support for ATOMIC_FENCE.Robert Lytton2013-11-121-0/+16
| | | | | | | | | | ATOMIC_FENCE is lowered to a compiler barrier which is codegen only. There is no need to emit an instructions since the XCore provides sequential consistency. Original patch by Richard Osborne llvm-svn: 194464
* XCore target: return error for unsupported alignmentRobert Lytton2013-11-121-0/+9
| | | | llvm-svn: 194463
* R600/SI: Change formatting of printed registers.Matt Arsenault2013-11-1253-280/+279
| | | | | | | | | | | | | | | | | | | | | | | Print the range of registers used with a single letter prefix. This better matches what the shader compiler produces and is overall less obnoxious than concatenating all of the subregister names together. Instead of SGPR0, it will print s0. Instead of SGPR0_SGPR1, it will print s[0:1] and so on. There doesn't appear to be a straightforward way to get the actual register info in the InstPrinter, so this parses the generated name to print with the new syntax. The required test changes are pretty nasty, and register matching regexes are now worse. Since there isn't a way to add to a variable in FileCheck, some of the tests now don't check the exact number of registers used, but I don't think that will be a real problem. llvm-svn: 194443
* Change the default branch instruction to be the 16 bit variety for mips16.Reed Kotler2013-11-121-0/+37
| | | | | | | | | | | This has no material effect at this time since we don't have a direct object emitter for mips16 and the assembler can't tell them apart. I place a comment "16 bit inst" for those so that I can tell them apart in the output. The constant island pass has only been minimally changed to allow this. More complete branch work is forthcoming but this is the first step. llvm-svn: 194442
* R600/SI: Add test that fails due to requiring i64 mul for pointersMatt Arsenault2013-11-111-0/+18
| | | | llvm-svn: 194433
* Fix the recently added anyregcc convention to handle spilled operands.Andrew Trick2013-11-111-8/+37
| | | | | | | | | | | | Fixes <rdar://15432754> [JS] Assertion: "Folded a def to a non-store!" The primary purpose of anyregcc is to prevent a patchpoint's call arguments and return value from being spilled. They must be available in a register, although the calling convention does not pin the register. It's up to the front end to avoid using this convention for calls with more arguments than allocatable registers. llvm-svn: 194428
* R600: Use function inputs to represent data stored in gprVincent Lejeune2013-11-1125-280/+246
| | | | llvm-svn: 194425
* [mips] Partially revert r193641. Stack alignment should not be determined byAkira Hatanaka2013-11-111-2/+1
| | | | | | | the floating point register mode. llvm-svn: 194423
* [NVPTX] Properly handle bitcast ConstantExpr when checking for the alignment ↵Justin Holewinski2013-11-111-0/+26
| | | | | | of function parameters llvm-svn: 194410
* [NVPTX] Fix logic error in loading vector parameters of more than 4 componentsJustin Holewinski2013-11-111-0/+13
| | | | llvm-svn: 194409
* [AArch64] The shift right/left and insert immediate builtins expect 3Chad Rosier2013-11-111-14/+18
| | | | | | source operands, a vector, an element to insert, and a shift amount. llvm-svn: 194406
* [AArch64] Add support for NEON scalar floating-point convert to fixed-point ↵Chad Rosier2013-11-111-8/+56
| | | | | | instructions. llvm-svn: 194394
* Vector forms of SHL, SRA, and SRL can be constant folded using ↵Daniel Sanders2013-11-111-0/+70
| | | | | | | | | | | | | | SimplifyVBinOp too Reviewers: dsanders Reviewed By: dsanders CC: llvm-commits, nadav Differential Revision: http://llvm-reviews.chandlerc.com/D1958 llvm-svn: 194393
* [mips][msa] CHECK-DAG-ize MSA 3r-a.ll test.Matheus Almeida2013-11-111-192/+336
| | | | | | No functional changes. llvm-svn: 194391
* [mips][msa] CHECK-DAG-ize MSA 2rf_int_float.ll test.Matheus Almeida2013-11-111-30/+50
| | | | | | No functional changes. llvm-svn: 194390
* [mips][msa] CHECK-DAG-ize MSA 2rf_float_int.ll test.Matheus Almeida2013-11-111-12/+20
| | | | | | No functional changes. llvm-svn: 194389
* [mips][msa] CHECK-DAG-ize MSA 2rf.ll test.Matheus Almeida2013-11-111-48/+80
| | | | | | No functional changes. llvm-svn: 194387
* [mips][msa] CHECK-DAG-ize MSA 2r.ll test.Matheus Almeida2013-11-111-36/+60
| | | | | | No functional changes. llvm-svn: 194386
* Add PPC option for full register names in asmHal Finkel2013-11-111-0/+17
| | | | | | | | | | | | | | | | | | | | | On non-Darwin PPC systems, we currently strip off the register name prefix prior to instruction printing. So instead of something like this: mr r3, r4 we print this: mr 3, 4 The first form is the default on Darwin, and is understood by binutils, but not yet understood by our integrated assembler. Once our integrated-as understands full register names as well, this temporary option will be replaced by tying this functionality to the verbose-asm option. The numeric-only form is compatible with legacy assemblers and tools, and is also gcc's default on most PPC systems. On the other hand, it is harder to read, and there are some analysis tools that expect full register names. llvm-svn: 194384
* Mostly finish up constant islands port for Mips for load constants.Reed Kotler2013-11-103-64/+344
| | | | | | | Still need to finish the branch part. Still lots more review of the code, clean up and testing. llvm-svn: 194337
* [mips] Make sure there is a chain edge dependency between loads that readAkira Hatanaka2013-11-092-7/+20
| | | | | | | | | formal arguments on the stack and stores created afterwards. We need this to ensure tail call optimized function calls do not write over the argument area of the stack before it is read out. llvm-svn: 194309
* [Stackmap] Materialize the jump address within the patchpoint noop slide.Juergen Ributzka2013-11-093-50/+36
| | | | | | | | | | | | | | | This patch moves the jump address materialization inside the noop slide. This enables patching of the materialization itself or its complete removal. This patch also adds the ability to define scratch registers that can be used safely by the code called from the patchpoint intrinsic. At least one scratch register is required, because that one is used for the materialization of the jump address. This patch depends on D2009. Differential Revision: http://llvm-reviews.chandlerc.com/D2074 Reviewed by Andy llvm-svn: 194306
* [Stackmap] Add AnyReg calling convention support for patchpoint intrinsic.Juergen Ributzka2013-11-081-0/+289
| | | | | | | | | | | | | | The idea of the AnyReg Calling Convention is to provide the call arguments in registers, but not to force them to be placed in a paticular order into a specified set of registers. Instead it is up tp the register allocator to assign any register as it sees fit. The same applies to the return value (if applicable). Differential Revision: http://llvm-reviews.chandlerc.com/D2009 Reviewed by Andy llvm-svn: 194293
* [VirtRegMap] Fix for PR17825. Do not ignore noreturn definitions when settingQuentin Colombet2013-11-081-4/+16
| | | | | | | isPhysRegUsed if the unwind information is required. Indeed, the runtime may need a correct stack to be able to unwind the call. llvm-svn: 194271
* ARM: fold prologue/epilogue sp updates into push/pop for code sizeTim Northover2013-11-081-0/+126
| | | | | | | | | | | | | | | | | | ARM prologues usually look like: push {r7, lr} sub sp, sp, #4 If code size is extremely important, this can be optimised to the single instruction: push {r6, r7, lr} where we don't actually care about the contents of r6, but pushing it subtracts 4 from sp as a side effect. This should implement such a conversion, predicated on the "minsize" function attribute (-Oz) since I've yet to find any code it actually makes faster. llvm-svn: 194264
* R600: Fix LowerUDIVREMVincent Lejeune2013-11-061-4/+17
| | | | llvm-svn: 194153
* Implement AArch64 Neon instruction set Perm.Jiangning Liu2013-11-061-0/+1676
| | | | llvm-svn: 194123
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