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* Fix handling of the 'n' asm constraint with invalid operands.James Y Knight2015-07-131-0/+10
| | | | | | | | | | It had accidently accepted a symbol+offset value (and emitted incorrect code for it, keeping only the offset part) instead of properly reporting the constraint as invalid. Differential Revision: http://reviews.llvm.org/D11039 llvm-svn: 242040
* AMDGPU/SI: Select mad patterns to v_mac_f32Tom Stellard2015-07-137-40/+200
| | | | | | | | | The two-address instruction pass will convert these back to v_mad_f32 if necessary. Differential Revision: http://reviews.llvm.org/D11060 llvm-svn: 242038
* ARM: Fix cttz expansion on vector types.Logan Chien2015-07-133-11/+473
| | | | | | | | | | | | The 64/128-bit vector types are legal if NEON instructions are available. However, there was no matching patterns for @llvm.cttz.*() intrinsics and result in fatal error. This commit fixes the problem by lowering cttz to: a. ctpop((x & -x) - 1) b. width - ctlz(x & -x) - 1 llvm-svn: 242037
* Print the visibility of available_externally functions.Rafael Espindola2015-07-131-0/+6
| | | | | | We were already printing it for declarations, but not available_externally. llvm-svn: 242027
* AVX-512: Added all AVX-512 forms of Vector Convert for Float/Double/Int/Long ↵Elena Demikhovsky2015-07-131-50/+0
| | | | | | | | | | | | types. In this patch I have only encoding. Intrinsics and DAG lowering will be in the next patch. I temporary removed the old intrinsics test (just to split this patch). Half types are not covered here. Differential Revision: http://reviews.llvm.org/D11134 llvm-svn: 242023
* [ARM] Add support for nest attribute using r12Renato Golin2015-07-121-0/+21
| | | | | | | | | | | | | | | | Register r12 ('ip') is used by GCC for this purpose and hence is used here. As discussed on the GCC mailing list, the register choice is an ABI issue and so choosing the same register as GCC means __builtin_call_with_static_chain is compatible. A similar patch has just gone in the AArch64 backend, so this is just the ARM counterpart, following the same discussion. Patch by Stephen Cross. llvm-svn: 241996
* [X86][SSE] Tidied up vector extend/truncation tests. NFCI.Simon Pilgrim2015-07-124-79/+81
| | | | llvm-svn: 241995
* [X86][SSE] Vectorized v4i32 non-uniform shifts.Simon Pilgrim2015-07-125-338/+238
| | | | | | | | | | While the v4i32 shl operation is already vectorized using a cvttps2dq/pmulld pattern, the lshr/ashr opeations are still scalarized. This patch adds vectorization support for non-uniform v4i32 shift operations - it splats constant shift amounts to allow them to use the immediate sse shift instructions, or extracts/zero-extends non-constant shift amounts. The individual results are then blended together. Differential Revision: http://reviews.llvm.org/D11063 llvm-svn: 241989
* [PowerPC] Make use of the TargetRecip systemHal Finkel2015-07-121-0/+15
| | | | | | | | | | r238842 added the TargetRecip system for controlling use of reciprocal estimates for sqrt and division using a set of parameters that can be set by the frontend. Clang now supports a sophisticated -mrecip option, and this will allow that option to effectively control the relevant code-generation functionality of the PPC backend. llvm-svn: 241985
* [PowerPC] Support the nest parameter attributeHal Finkel2015-07-122-0/+68
| | | | | | | | | | | | | This adds support for the 'nest' attribute, which allows the static chain register to be set for functions calls under non-Darwin PPC/PPC64 targets. r11 is the chain register (which the PPC64 ELF ABI calls the "environment pointer"). For indirect calls under PPC64 ELFv1, this would normally be loaded from the function descriptor, but providing an explicit 'nest' parameter will override that process and use the value provided. This allows __builtin_call_with_static_chain to work as expected on PowerPC. llvm-svn: 241984
* MIR Serialization: Serialize the virtual register operands.Alex Lorenz2015-07-102-4/+102
| | | | | | | | Reviewers: Duncan P. N. Exon Smith Differential Revision: http://reviews.llvm.org/D11005 llvm-svn: 241959
* [SEH] Push reloads of the SEH code past phi nodesReid Kleckner2015-07-101-0/+91
| | | | | | | | | | | This in turn would sometimes introduce new cleanupblocks that didn't previously exist. The uses were being introduced by SSA value demotion. We actually want to *promote* uses of EH pointers and selectors, so I added some spcecial casing to avoid demoting such instructions. This is getting overly complicated, but hopefully we'll come along and delete it in the new representation. llvm-svn: 241950
* DAGCombiner: Assume invariant load cannot alias a storeMatt Arsenault2015-07-101-0/+35
| | | | | | | | | | The motivation is to allow GatherAllAliases / FindBetterChain to not give up on dependent loads of a pointer from constant memory. This is important for AMDGPU, because most loads are pointers derived from a load of a kernel argument from constant memory. llvm-svn: 241948
* [ShrinkWrap][PEI] Do not insert epilogue for unreachable blocks.Quentin Colombet2015-07-102-0/+78
| | | | | | | Although this is not incorrect to insert such code, it is useless and it hurts the binary size. llvm-svn: 241946
* Fix AArch64 prologue for empty frame with dynamic allocas.Evgeniy Stepanov2015-07-101-0/+50
| | | | | | | | Fixes PR23804: assertion failure in emitPrologue in the case of a function with an empty frame and a dynamic alloca that needs stack realignment. This is a typical case for AddressSanitizer. llvm-svn: 241943
* ARMLoadStoreOpt: Merge subs/adds into LDRD/STRD; Factor out common codeMatthias Braun2015-07-101-4/+52
| | | | | | | | | | | | This commit factors out common code from MergeBaseUpdateLoadStore() and MergeBaseUpdateLSMultiple() and introduces a new function MergeBaseUpdateLSDouble() which merges adds/subs preceding/following a strd/ldrd instruction into an strd/ldrd instruction with writeback where possible. Differential Revision: http://reviews.llvm.org/D10676 llvm-svn: 241928
* ComputeKnownBits: be a bit smarter about ADDsFiona Glaser2015-07-102-7/+8
| | | | | | | | If our two inputs have known top-zero bit counts M and N, we trivially know that the output cannot have any bits set in the top (min(M, N)-1) bits, since nothing could carry past that point. llvm-svn: 241927
* ARMLoadStoreOptimizer: Create LDRD/STRD on thumb2Matthias Braun2015-07-106-16/+36
| | | | | | Differential Revision: http://reviews.llvm.org/D10623 llvm-svn: 241926
* MIR Serialization: Initial serialization of stack objects.Alex Lorenz2015-07-101-0/+39
| | | | | | | | | | | | | | This commit implements the initial serialization of stack objects from the MachineFrameInfo class. It can only serialize the ordinary stack objects (including ordinary spill slots), but it doesn't serialize variable sized or fixed stack objects yet. The stack objects are serialized using a YAML sequence of YAML inline mappings. Each mapping has the object's ID, type, size, offset and alignment. The stack objects are a part of machine function's YAML mapping. Reviewers: Duncan P. N. Exon Smith llvm-svn: 241922
* ARMLoadStoreOptimizer: Rewrite LDM/STM matching logic.Matthias Braun2015-07-101-2/+2
| | | | | | | | | | | | | | | | | | | | | This improves the logic in several ways and is a preparation for followup patches: - First perform an analysis and create a list of merge candidates, then transform. This simplifies the code in that you have don't have to care to much anymore that you may be holding iterators to MachineInstrs that get removed. - Analyze/Transform basic blocks in reverse order. This allows to use LivePhysRegs to find free registers instead of the RegisterScavenger. The RegisterScavenger will become less precise in the future as it relies on the deprecated kill-flags. - Return the newly created node in MergeOps so there's no need to look around in the schedule to find it. - Rename some MBBI iterators to InsertBefore to make their role clear. - General code cleanup. Differential Revision: http://reviews.llvm.org/D10140 llvm-svn: 241920
* Actually support volatile memcpys in NVPTX loweringEli Bendersky2015-07-101-0/+13
| | | | | | Differential Revision: http://reviews.llvm.org/D11091 llvm-svn: 241914
* [NVPTX] declare no vector registersJingyue Wu2015-07-101-0/+39
| | | | | | | | | | | | | | | | | Summary: Without this patch, LoopVectorizer in certain cases (see loop-vectorize.ll) produces code with complex control flow which hurts later optimizations. Since NVPTX doesn't have vector registers in LLVM's sense (NVPTXTTI::getRegisterBitWidth(true) == 32), we for now declare no vector registers to effectively disable loop vectorization. Reviewers: jholewinski Subscribers: jingyue, llvm-commits, jholewinski Differential Revision: http://reviews.llvm.org/D11089 llvm-svn: 241884
* [WinEH] Make sure LSDA tables are 4 byte alignedReid Kleckner2015-07-105-0/+6
| | | | | | | | | | Apparently this is important, otherwise _except_handler3 assumes that the registration node is corrupted and ignores it. Also fix a bug in WinEHPrepare where we would insert code after a terminator instruction. llvm-svn: 241877
* [x86] enable machine combiner reassociations for scalar double-precision ↵Sanjay Patel2015-07-091-0/+23
| | | | | | multiplies llvm-svn: 241873
* [x86] enable machine combiner reassociations for scalar double-precision addsSanjay Patel2015-07-091-1/+23
| | | | llvm-svn: 241871
* MIR Serialization: Serialize the virtual register definitions.Alex Lorenz2015-07-092-0/+61
| | | | | | | | | | | | The virtual registers are serialized using a YAML sequence of YAML inline mappings. Each mapping has the id of the virtual register and the register class. Reviewers: Duncan P. N. Exon Smith Differential Revision: http://reviews.llvm.org/D10981 llvm-svn: 241868
* [WinEH] Give up on using CSRs across 32-bit invokes for nowReid Kleckner2015-07-092-23/+37
| | | | | | | | | | | The runtime does not restore CSRs when transferring control back to the function handling the exception. According to the experts on IRC, LLVM's register allocator has no way to model register clobbers that only happen on one edge of the CFG. For now, don't worry about trying to use the meager three CSRs available on 32-bit X86 and just say that such invokes preserve nothing. llvm-svn: 241865
* MIR Parser: Report an error when parsing machine function with an empty body.Alex Lorenz2015-07-097-0/+39
| | | | | | | | | | This commit adds a new error which is reported when the MIR Parser encounters a machine function without any machine basic blocks. The machine verifier expects that the machine functions have at least one MBB, and this error will prevent machine functions without MBBs from reaching the machine verifier and crashing with an assertion. llvm-svn: 241862
* [ImplicitNullChecks] Be smarter in picking the memory op.Sanjoy Das2015-07-092-2/+84
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: Before this change ImplicitNullChecks would only pick loads of the form: ``` test Reg, Reg jz elsewhere fallthrough: movl 32(Reg), Reg2 ``` but not (say) ``` test Reg, Reg jz elsewhere fallthrough: inc Reg3 movl 32(Reg), Reg2 ``` This change teaches ImplicitNullChecks to look through "unrelated" instructions like `inc Reg3` when searching for a load instruction to convert to a trapping load. Reviewers: atrick, JosephTremoulet, reames Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D11044 llvm-svn: 241850
* MIR Serialization: Serialize the simple MachineFrameInfo attributes.Alex Lorenz2015-07-091-0/+91
| | | | | | | | | | | | This commit serializes the 13 scalar boolean and integer attributes from the MachineFrameInfo class: IsFrameAddressTaken, IsReturnAddressTaken, HasStackMap, HasPatchPoint, StackSize, OffsetAdjustment, MaxAlignment, AdjustsStack, HasCalls, MaxCallFrameSize, HasOpaqueSPAdjustment, HasVAStart, and HasMustTailInVarArgFunc. These attributes are serialized as part of the frameInfo YAML mapping, which itself is a part of the machine function's YAML mapping. llvm-svn: 241844
* Allow {e,r}bp as the target of {read,write}_register.Pat Gavlin2015-07-092-0/+42
| | | | | | | | | | This patch allows the read_register and write_register intrinsics to read/write the RBP/EBP registers on X86 iff the targeted register is the frame pointer for the containing function. Differential Revision: http://reviews.llvm.org/D10977 llvm-svn: 241827
* fix an invisible bug when combining repeated FP divisorsSanjay Patel2015-07-091-0/+17
| | | | | | | | | | | | | | | | | | | | | | | This patch fixes bugs that were exposed by the addition of fast-math-flags in the DAG: r237046 ( http://reviews.llvm.org/rL237046 ): 1. When replacing a division node, it's not enough to RAUW. We should call CombineTo() to delete dead nodes and combine again. 2. Because we are changing the DAG, we can't return an empty SDValue after the transform. As the code comments say: Visitation implementation - Implement dag node combining for different node types. The semantics are as follows: Return Value: SDValue.getNode() == 0 - No change was made SDValue.getNode() == N - N was replaced, is dead and has been handled. otherwise - N should be replaced by the returned Operand. The new test case shows no difference with or without this patch, but it will crash if we re-apply r237046 or enable FMF via the current -enable-fmf-dag cl::opt. Differential Revision: http://reviews.llvm.org/D9893 llvm-svn: 241826
* Reapply fixed r241790: Fix shift legalization and lowering for big constants.Pawel Bylica2015-07-091-0/+44
| | | | | | | | | | | | Summary: If shift amount is a constant value > 64 bit it is handled incorrectly during type legalization and X86 lowering. This patch the type of shift amount argument in function DAGTypeLegalizer::ExpandShiftByConstant from unsigned to APInt. Reviewers: nadav, majnemer, sanjoy, RKSimon Subscribers: RKSimon, llvm-commits Differential Revision: http://reviews.llvm.org/D10767 llvm-svn: 241806
* [Hexagon] Add support for atomic RMW operationsKrzysztof Parzyszek2015-07-091-0/+71
| | | | llvm-svn: 241804
* [AArch64] Select SBFIZ or UBFIZ instead of left + right shiftsArnaud A. de Grandmaison2015-07-091-0/+33
| | | | | | And rename LSB to Immr / MSB to Imms to match the ARM ARM terminology. llvm-svn: 241803
* Test for 241794 (nest attribute in AArch64)Renato Golin2015-07-091-0/+23
| | | | | | | | Forgot to git add the test. Patch by Stephen Cross. llvm-svn: 241797
* Revert r241790: Fix shift legalization and lowering for big constants.Pawel Bylica2015-07-091-44/+0
| | | | llvm-svn: 241792
* Fix shift legalization and lowering for big constants.Pawel Bylica2015-07-091-0/+44
| | | | | | | | | | | | Summary: If shift amount is a constant value > 64 bit it is handled incorrectly during type legalization and X86 lowering. This patch the type of shift amount argument in function DAGTypeLegalizer::ExpandShiftByConstant from unsigned to APInt. Reviewers: nadav, majnemer, sanjoy, RKSimon Subscribers: RKSimon, llvm-commits Differential Revision: http://reviews.llvm.org/D10767 llvm-svn: 241790
* Extended syntax of vector version of getelementptr instruction.Elena Demikhovsky2015-07-091-0/+22
| | | | | | | | | | | | | | | | | | | | | | | | | | The justification of this change is here: http://lists.cs.uiuc.edu/pipermail/llvmdev/2015-March/082989.html According to the current GEP syntax, vector GEP requires that each index must be a vector with the same number of elements. %A = getelementptr i8, <4 x i8*> %ptrs, <4 x i64> %offsets In this implementation I let each index be or vector or scalar. All vector indices must have the same number of elements. The scalar value will mean the splat vector value. (1) %A = getelementptr i8, i8* %ptr, <4 x i64> %offsets or (2) %A = getelementptr i8, <4 x i8*> %ptrs, i64 %offset In all cases the %A type is <4 x i8*> In the case (2) we add the same offset to all pointers. The case (1) covers C[B[i]] case, when we have the same base C and different offsets B[i]. The documentation is updated. http://reviews.llvm.org/D10496 llvm-svn: 241788
* MIR Serialization: Serialize the 'undef' register machine operand flag.Alex Lorenz2015-07-081-0/+42
| | | | llvm-svn: 241762
* [x86] enable machine combiner reassociations for scalar single-precision ↵Sanjay Patel2015-07-083-6/+27
| | | | | | multiplies llvm-svn: 241752
* Add tests for the NVPTXLowerAggrCopies pass.Eli Bendersky2015-07-081-0/+34
| | | | | | | Note: not testing memmove lowering for now, as it's broken [see https://llvm.org/bugs/show_bug.cgi?id=24056] llvm-svn: 241736
* MIR Serialization: Serialize the 'killed' register machine operand flag.Alex Lorenz2015-07-081-0/+42
| | | | llvm-svn: 241734
* [X86][SSE] Vector shift test cleanup. NFC.Simon Pilgrim2015-07-086-1280/+1280
| | | | llvm-svn: 241730
* [Win64] Only treat some functions as having the Win64 conventionReid Kleckner2015-07-081-0/+18
| | | | | | | | | | | | | | | | All the usual X86 target-specific conventions are collapsed to the normal Win64 convention, but the custom conventions like GHC and webkit should not be. Previously we would assume that the caller allocated 32 bytes of shadow space for us, which is not how webkit_jscc or other custom conventions are supposed to work. Based on a patch by peavo@outlook.com. Fixes PR24051. llvm-svn: 241725
* MIR Parser: Use source locations for MBB naming errors.Alex Lorenz2015-07-081-1/+1
| | | | | | | | | This commit changes the type of the field 'Name' in the struct 'yaml::MachineBasicBlock' from 'std::string' to 'yaml::StringValue'. This change allows the MIR parser to report errors related to the MBB name with the proper source locations. llvm-svn: 241718
* [Hexagon] Implement commoning of GetElementPtr instructionsKrzysztof Parzyszek2015-07-082-0/+113
| | | | llvm-svn: 241714
* [SEH] Add missing test case from previous realignment commitReid Kleckner2015-07-081-0/+101
| | | | llvm-svn: 241700
* [SEH] Ensure that empty __except blocks have their own BBReid Kleckner2015-07-081-0/+32
| | | | | | | | | The 32-bit lowering assumed that WinEHPrepare had this invariant. WinEHPrepare did it for C++, but not SEH. The result was that we would insert calls to llvm.x86.seh.restoreframe in normal basic blocks, which corrupted the frame pointer. llvm-svn: 241699
* [SPARC] Cleanup handling of the Y/ASR registers.James Y Knight2015-07-082-1/+22
| | | | | | | | | | | | | | | | | | - Implement copying ASR to/from GPR regs. - Mark ASRs as non-allocatable, so it won't try to arbitrarily use them inappropriately. - Instead of inserting explicit WRASR/RDASR nodes in the MUL/DIV routines, just do normal register copies. - Also...mark div as using Y, not just writing it. Added a test case with some code which previously died with an assertion failure (with -O0), or produced wrong code (otherwise). (Third time's the charm?) Differential Revision: http://reviews.llvm.org/D10401 llvm-svn: 241686
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