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* [X86][NFC] Add proper test for promotion of i8 cmov's of trunc'sRoman Lebedev2019-03-051-0/+271
| | | | | | | There was no proper test for that code in X86TargetLowering::LowerSELECT(). Noticed accidentally while trying to modify the last branch in that function. llvm-svn: 355452
* [WebAssembly] Disable MachineBlockPlacement passHeejin Ahn2019-03-055-430/+71
| | | | | | | | | | | | | | | | | Summary: This pass hurts code size for wasm and sometimes generates irreducible control flow. Context: https://github.com/emscripten-core/emscripten/pull/8233 Reviewers: kripken, dschuff Subscribers: sunfish, sbc100, jgravelle-google, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D58953 llvm-svn: 355437
* [NFC][CodeGen][X86][AArch64] Add tests for C++ std::midpoint() pattern (PR40965)Roman Lebedev2019-03-055-0/+10752
| | | | | | | | | | | | | Tests only for integers, not floating point or pointers. The scalar 8-bit case uses branch instead of CMOV, because there is no no 8-bit CMOV. Vector tests are for consistency, since it can be vectorized. https://bugs.llvm.org/show_bug.cgi?id=40965 llvm-svn: 355436
* AMDGPU: Preserve undef flag when expanding SI_IFMatt Arsenault2019-03-051-8/+38
| | | | | | Fixes undefined value verifier error. llvm-svn: 355426
* [X86] Enable 8-bit SHL to convert to LEACraig Topper2019-03-052-8/+8
| | | | | | Differential Revision: https://reviews.llvm.org/D58870 llvm-svn: 355425
* [X86] Allow 8-bit INC/DEC to be converted to LEA.Craig Topper2019-03-052-12/+10
| | | | | | | | We already do this for 16/32/64 as well as 8-bit add with register/immediate. Might as well do it for 8-bit INC/DEC too. Differential Revision: https://reviews.llvm.org/D58869 llvm-svn: 355424
* [X86] Enable 8-bit OR with disjoint bits to convert to LEACraig Topper2019-03-0510-93/+113
| | | | | | | | We already support 8-bits adds in convertToThreeAddress. But we can also support 8-bit OR if the bits are disjoint. We already do this for 16/32/64. Differential Revision: https://reviews.llvm.org/D58863 llvm-svn: 355423
* [X86][SSE] Regenerate vector zero testsSimon Pilgrim2019-03-051-16/+51
| | | | llvm-svn: 355412
* Revert "[GlobalISel][AArch64] Add selection support for G_EXTRACT_VECTOR_ELT"Jessica Paquette2019-03-052-197/+0
| | | | | | | | | | | This broke test-suite::aarch64_neon_intrinsics.test Reverting while I look into it. Example failure: http://lab.llvm.org:8011/builders/clang-cmake-aarch64-quick/builds/17740 llvm-svn: 355408
* [X86] Add SMULO/UMULO combine testsSimon Pilgrim2019-03-051-0/+136
| | | | | | Include scalar and vector test variants covering the folds in DAGCombiner (vector isn't currently supported - PR40442) llvm-svn: 355407
* Fix typo in constant vectorSimon Pilgrim2019-03-051-4/+4
| | | | llvm-svn: 355405
* [X86] Add SADDO/UADDO and SSUBO/USUBO combine testsSimon Pilgrim2019-03-052-0/+464
| | | | | | Include scalar and vector test variants covering the folds in DAGCombiner (vector isn't currently supported - PR40442) llvm-svn: 355404
* [X86] Add test cases for D58874Simon Pilgrim2019-03-051-0/+45
| | | | | | Add scalar and vector test cases for missing (add (add (xor a, -1), b), 1) -> (sub b, a) fold llvm-svn: 355400
* [AMDGPU] Fix DPP operand order in atomic optimizerCarl Ritson2019-03-055-6/+15
| | | | | | | | | | | | | | | | | | | Summary: Ensure order of operands in DPP atomic optimizer final WWM step is appropriate for sub instructions. Change-Id: I631d050e1c00a3b4bc7c11a90437064403c4cf30 Reviewers: sheredom, tpr Reviewed By: sheredom Subscribers: arsenm, kzhuravl, jvesely, wdng, nhaehnle, yaxunl, dstuttard, t-tye, jfb, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D58900 llvm-svn: 355394
* [ARM] Fix select_cc lowering for fp16Oliver Stannard2019-03-051-0/+676
| | | | | | | | | | | When lowering a select_cc node where the true and false values are of type f16, we can't use a general conditional move because the FP16 instructions do not support conditional execution. Instead, we must ensure that the condition code is one of the four supported by the VSEL instruction. Differential revision: https://reviews.llvm.org/D58813 llvm-svn: 355385
* [AMDGPU] Omit KILL instructions from hazard recognizerDavid Stuttard2019-03-051-0/+32
| | | | | | | | | | | | | | | | | | Summary: In some cases the KILL was causing a hazard to be introduced as these were scheduled into hazard slots, but don't result in an instruction. KILL shouldn't be considered for hazard recognition. Change-Id: Ib6d2a2160f8c94cd0ce611ab198c7e4f46aeffcf Subscribers: arsenm, kzhuravl, jvesely, wdng, nhaehnle, yaxunl, tpr, t-tye, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D58898 llvm-svn: 355384
* [PowerPC] fix killed/dead flag after convert x-form to d-form tranformation.Chen Zheng2019-03-052-1/+184
| | | | | | Differential Revision: https://reviews.llvm.org/D58428 llvm-svn: 355378
* [BPF] Do not generate BTF sections unnecessarilyYonghong Song2019-03-0531-331/+22
| | | | | | | | | | | | If There is no types/non-empty strings, do not generate .BTF section. If there is no func_info/line_info, do not generate .BTF.ext section. Signed-off-by: Yonghong Song <yhs@fb.com> Differential Revision: https://reviews.llvm.org/D58936 llvm-svn: 355360
* Fix invalid target triples in tests. (NFC)Florian Hahn2019-03-042-3/+3
| | | | llvm-svn: 355349
* [GlobalISel][AArch64] Add selection support for G_EXTRACT_VECTOR_ELTJessica Paquette2019-03-042-0/+197
| | | | | | | | | | | | | This adds instruction selection support for G_EXTRACT_VECTOR_ELT for cases where the index is defined by a G_CONSTANT. It also factos out the lane copy opcode selection part into its own function, `getLaneCopyOpcode`. This is used by both `selectUnmergeValues` and `selectExtractElt`. Differential Revision: https://reviews.llvm.org/D58469 llvm-svn: 355344
* [GlobalISel][AArch64] Legalize vector G_SELECTJessica Paquette2019-03-041-0/+69
| | | | | | | | Just scalarize it, and add a test showing it works. Differential Revision: https://reviews.llvm.org/D58747 llvm-svn: 355339
* Re-commit r355104: "[AArch64][GlobalISel] Add support for 64 bit vector ↵Amara Emerson2019-03-041-25/+49
| | | | | | | | | | | | shuffle using TBL1." The code to materialize a mask from a constant pool load tried to use a 128 bit LDR to load a 64 bit constant pool entry, which was 8 byte aligned. This resulted in a link failure in the NEON tests in the test suite since the LDR address was unaligned. This change fixes that to instead emit a 64 bit LDR if the entry is 64 bit, before converting back to a 128 bit register for the TBL. llvm-svn: 355326
* [DAGCombiner][X86][SystemZ][AArch64] Combine some cases of (bitcast ↵Craig Topper2019-03-0414-109/+63
| | | | | | | | | | (build_vector constants)) between legalize types and legalize dag. This patch enables combining integer bitcasts of integer build vectors when the new scalar type is legal. I've avoided floating point because the implementation bitcasts float to int along the way and we would need to check the intermediate types for legality Differential Revision: https://reviews.llvm.org/D58884 llvm-svn: 355324
* [X86] Regenerate illegal type load test with non-undef load address.Simon Pilgrim2019-03-041-6/+6
| | | | | | This would be affected by an upcoming patch without undoing some of the bugpoint reduction. llvm-svn: 355316
* [X86] Avoid codegen changes when DBG_VALUE appears between lowered selectsJeremy Morse2019-03-041-0/+50
| | | | | | | | | | | | | | | | X86TargetLowering::EmitLoweredSelect presently detects sequences of CMOV pseudo instructions without accounting for debug intrinsics. This leads to different codegen with and without option -g, if a DBG_VALUE instruction lands in the middle of several lowered selects. Work around this by skipping over debug instructions when looking for CMOV sequences, and sinking those debug insts into the EmitLoweredSelect sunk block. This might slightly shift where variables appear in the instruction sequence, but won't re-order assignments. Differential Revision: https://reviews.llvm.org/D58672 llvm-svn: 355307
* [ARM] Fix selection of VLDR.16 instruction with imm offsetOliver Stannard2019-03-041-0/+105
| | | | | | | | | | | | The isScaledConstantInRange function takes upper and lower bounds which are checked after dividing by the scale, so the bounds checks for half, single and double precision should all be the same. Previously, we had wrong bounds checks for half precision, so selected an immediate the instructions can't actually represent. Differential revision: https://reviews.llvm.org/D58822 llvm-svn: 355305
* [WebAssembly] Delete ThrowUnwindDest map from WasmEHFuncInfoHeejin Ahn2019-03-031-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: Before when we implemented the first EH proposal, 'catch <tag>' instruction may not catch an exception so there were multiple EH pads an exception can unwind to. That means a BB could have multiple EH pad successors. Now after we switched to the new proposal, every 'catch' instruction catches an exception, and there is only one catchpad per catchswitch, so we at most have one EH pad successor, making `ThrowUnwindDest` map in `WasmEHInfo` unnecessary. Keeping `ThrowUnwindDest` map in `WasmEHInfo` has its own problems, because other optimization passes can split a BB that contains possibly throwing calls (previously invokes), and we have to update the map every time that happens, which is not easy for common CodeGen passes. This also correctly updates successor info in LateEHPrepare when we add a rethrow instruction. Reviewers: dschuff Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D58486 llvm-svn: 355296
* [X86] Regenerate test to get the full FP operands printed. NFCCraig Topper2019-03-031-2/+2
| | | | | | Missed when I updated the printer to print implicit %st operand on binops. llvm-svn: 355295
* [X86] getShuffleScalarElt - peek through insert/extract subvector nodes.Simon Pilgrim2019-03-031-10/+0
| | | | llvm-svn: 355288
* [X86] Prefer VPBLENDD for v2i64/v4i64 blends with AVX2.Craig Topper2019-03-039-80/+170
| | | | | | | | We were using VPBLENDW for v2i64 and VBLENDPD for v4i64. VPBLENDD has better throughput than VPBLENDW on some CPUs so it makes sense to use it when possible. VBLENDPD will probably become VBLENDD during execution domain fixing, but we might as well use integer in isel while we can. This should work around some issues with the domain fixing pass prefering PBLENDW when we start with PBLENDW. There may still be some v8i16 cases that could use PBLENDD. llvm-svn: 355281
* Add test case for add to sub transformation. NFCAmaury Sechet2019-03-021-0/+30
| | | | llvm-svn: 355269
* [Codegen] fix typos in test caseXing GUO2019-03-023-5/+5
| | | | llvm-svn: 355264
* [WebAssembly] Expand operations not supported by SIMDThomas Lively2019-03-021-0/+450
| | | | | | | | | | | | | | | | | | Summary: This prevents crashes in instruction selection when these operations are used. The tests check that the scalar version of the instruction is used where applicable, although some expansions do not use the scalar version. Reviewers: aheejin Subscribers: dschuff, sbc100, jgravelle-google, hiraditya, sunfish, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D58859 llvm-svn: 355261
* [X86] Improve use of SHLD/SHRDAmaury Sechet2019-03-022-25/+9
| | | | | | | | | | | | | | | Summary: This extends the variety of pattern that can generate a SHLD instead of using two shifts. This fixes a regression that would be introduced by D57367 or D33587 Reviewers: RKSimon, craig.topper Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D57389 llvm-svn: 355260
* Add test case for truncate funnel shifts. NFCAmaury Sechet2019-03-022-0/+62
| | | | llvm-svn: 355258
* Revert "[MIPS GlobalISel] Fix mul operands"Vlad Tsyrklevich2019-03-014-56/+35
| | | | | | | This reverts commit r355178, it is causing ASan failures on the sanitizer bots. llvm-svn: 355219
* [ARM] Fix FP16 stack loads/stores for Thumb2 with frame pointerOliver Stannard2019-03-011-0/+22
| | | | | | | | | | The new addressing mode added for the v8.2A FP16 instructions uses bit 8 of the immediate to encode the sign of the offset, like the other FP loads/stores, so need to be treated the same way. Differential revision: https://reviews.llvm.org/D58816 llvm-svn: 355201
* [ARM] Consider undefined-on-NaN conditions in checkVSELConstraintsOliver Stannard2019-03-011-34/+251
| | | | | | | | | | This function was not checking for the condition code variants which are undefined if either input is NaN, so we were missing selection of the VSEL instruction in some cases when using -fno-honor-nans or -ffast-math. Differential revision: https://reviews.llvm.org/D58812 llvm-svn: 355199
* [X86] Regenerate legalize test filesSimon Pilgrim2019-03-012-84/+151
| | | | | | Noticed while getting update_mir_test_checks.py to work on python3 llvm-svn: 355198
* [Thumb] Add some integer abs testcases for different typesizes.Simon Pilgrim2019-03-011-15/+53
| | | | | | | | Committed on behalf of @ikulagin (Ivan Kulagin) Differential Revision: https://reviews.llvm.org/D52138 llvm-svn: 355197
* [ARM GlobalISel] Support G_CTLZ for Thumb2Diana Picus2019-03-012-0/+34
| | | | | | Same as ARM mode but with different opcode. llvm-svn: 355191
* [ARM GlobalISel] Check target flags in test. NFCIDiana Picus2019-03-012-12/+12
| | | | | | | | There was a time when we couldn't dump target-specific flags such as arm-sbrel etc, so the tests didn't check for them. We can now be more specific in our tests. llvm-svn: 355189
* [AMDGPU] Mark ds instructions as meybeAtomicStanislav Mekhanoshin2019-03-011-46/+46
| | | | | | | | | | | | These were not recognized as potential atomics by memory legalizer. The test was working not because legalizer did a right thing, but because it has skipped all these instructions. When I have fixed DS desciption test started to fail because region address has changed from 4 to 2 a while ago. Differential Revision: https://reviews.llvm.org/D58802 llvm-svn: 355179
* [MIPS GlobalISel] Fix mul operandsPetar Avramovic2019-03-014-35/+56
| | | | | | | | | | | | | | | | | Unsigned mul high for MIPS32 is selected into two PseudoInstructions: PseudoMULTu and PseudoMFHI that use accumulator register class ACC64 for some of its operands. Registers in this class have appropriate hi and lo register as subregisters: $lo0 and $hi0 are subregisters of $ac0 etc. mul instruction implicit-defs $lo0 and $hi0 according to MipsInstrInfo.td. In functions where mul and PseudoMULTu are present fastRegisterAllocator will "run out of registers during register allocation" because 'calcSpillCost' for $ac0 will return spillImpossible because subregisters $lo0 and $hi0 of $ac0 are reserved by mul instruction above. A solution is to mark implicit-defs of $lo0 and $hi0 as dead in mul instruction. Differential Revision: https://reviews.llvm.org/D58715 llvm-svn: 355178
* [MIPS GlobalISel] Select G_UMULHPetar Avramovic2019-03-014-0/+128
| | | | | | | | Legalize G_UMULO and select G_UMULH for MIPS32. Differential Revision: https://reviews.llvm.org/D58714 llvm-svn: 355177
* AMDGPU/GlobalISel: Implement select for G_INSERTTom Stellard2019-03-011-0/+49
| | | | | | | | | | | | Re-commit r344310. Reviewers: arsenm Subscribers: kzhuravl, jvesely, wdng, nhaehnle, yaxunl, rovka, kristof.beyls, dstuttard, tpr, t-tye, llvm-commits Differential Revision: https://reviews.llvm.org/D53116 llvm-svn: 355159
* [WebAssembly] Fix crash when @llvm.global_dtors is externalThomas Lively2019-03-011-0/+9
| | | | | | | | | | | | Reviewers: aheejin Subscribers: dschuff, sbc100, jgravelle-google, hiraditya, sunfish, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D58799 llvm-svn: 355157
* AMDGPU/GlobalISel: Implement select for G_EXTRACTTom Stellard2019-02-281-0/+77
| | | | | | | | | | Reviewers: arsenm Subscribers: kzhuravl, wdng, nhaehnle, yaxunl, rovka, kristof.beyls, dstuttard, tpr, t-tye, llvm-commits Differential Revision: https://reviews.llvm.org/D49714 llvm-svn: 355156
* [AArch64] [Windows] Don't skip constructing UnwindHelp.Eli Friedman2019-02-283-6/+46
| | | | | | | | | | | | | In certain cases, the first non-frame-setup instruction in a function is a branch. For example, it could be a cbz on an argument. Make sure we correctly allocate the UnwindHelp, and find an appropriate register to use to initialize it. Fixes https://bugs.llvm.org/show_bug.cgi?id=40184 Differential Revision: https://reviews.llvm.org/D58752 llvm-svn: 355136
* [AArch64] Improve FP16 vector convert from short instructions.Abderrazek Zaafrani2019-02-282-28/+33
| | | | | | https://reviews.llvm.org/D58563 llvm-svn: 355134
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