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* Fix an obvious typo which caused an isel assertion. rdar://8964854.Evan Cheng2011-02-071-0/+17
| | | | llvm-svn: 125023
* Reduce test case, smaller is better.Devang Patel2011-02-071-789/+33
| | | | llvm-svn: 125019
* Add codegen support for using post-increment NEON load/store instructions.Bob Wilson2011-02-0711-0/+381
| | | | | | | | The vld1-lane, vld1-dup and vst1-lane instructions do not yet support using post-increment versions, but all the rest of the NEON load/store instructions should be handled now. llvm-svn: 125014
* Rework some .ARM.attribute work for improved gcc compatibility.Jason W Kim2011-02-072-17/+35
| | | | | | | Unified EmitTextAttribute for both Asm and Obj emission (.cpu only) Added necessary cortex-A8 related attrs for codegen compat tests. llvm-svn: 124995
* Target/X86: Tweak allocating shadow area (aka home) on Win64. It must be ↵NAKAMURA Takumi2011-02-054-20/+17
| | | | | | enough for caller to allocate one. llvm-svn: 124949
* Move a test that ended up in the wrong place.Bob Wilson2011-02-052-18/+18
| | | | llvm-svn: 124933
* Merge .debug_loc entries whenever possible to reduce debug_loc size.Devang Patel2011-02-041-0/+827
| | | | llvm-svn: 124904
* Mark that the return is using EAX so that we don't use it for some otherNick Lewycky2011-02-041-0/+14
| | | | | | purpose. Fixes PR9080! llvm-svn: 124903
* DebugLoc associated with a machine instruction is used to emit location ↵Devang Patel2011-02-042-2/+72
| | | | | | entries. DebugLoc associated with a DBG_VALUE is used to identify lexical scope of the variable. After register allocation, while inserting DBG_VALUE remember original debug location for the first instruction and reuse it, otherwise dwarf writer may be mislead in identifying the variable's scope. llvm-svn: 124845
* Add XCore intrinsics for resource instructions.Richard Osborne2011-02-031-0/+97
| | | | llvm-svn: 124794
* Add -march to fix the bots.Rafael Espindola2011-02-031-1/+1
| | | | llvm-svn: 124774
* Fix PR9127 by reversing the operands even if they have more then one use.Rafael Espindola2011-02-031-0/+12
| | | | | | | | Reversing the operands allows us to fold, but doesn't force us to. Also, at this point the DAG is still being optimized, so the check for hasOneUse is not very precise. llvm-svn: 124773
* Add support for trampolines on the XCore.Richard Osborne2011-02-021-0/+37
| | | | llvm-svn: 124722
* Given a pair of floating point load and store, if there are no other uses ofEvan Cheng2011-02-021-0/+28
| | | | | | | | | | | | | | | | | | | the load, then it may be legal to transform the load and store to integer load and store of the same width. This is done if the target specified the transformation as profitable. e.g. On arm, this can transform: vldr.32 s0, [] vstr.32 s0, [] to ldr r12, [] str r12, [] rdar://8944252 llvm-svn: 124708
* Keep track of incoming argument's location while emitting LiveIns.Devang Patel2011-01-311-0/+84
| | | | llvm-svn: 124611
* Fix bug where ReduceLoadWidth was creating illegal ZEXTLOAD instructions.Richard Osborne2011-01-311-0/+10
| | | | llvm-svn: 124587
* Teach DAGCombine to fold fold (sra (trunc (sr x, c1)), c2) -> (trunc (sra x, ↵Benjamin Kramer2011-01-301-0/+9
| | | | | | | | | | | | | | | | | | c1+c2) when c1 equals the amount of bits that are truncated off. This happens all the time when a smul is promoted to a larger type. On x86-64 we now compile "int test(int x) { return x/10; }" into movslq %edi, %rax imulq $1717986919, %rax, %rax movq %rax, %rcx shrq $63, %rcx sarq $34, %rax <- used to be "shrq $32, %rax; sarl $2, %eax" addl %ecx, %eax This fires 96 times in gcc.c on x86-64. llvm-svn: 124559
* Re-apply r124518 with fix. Watch out for invalidated iterator.Evan Cheng2011-01-291-5/+6
| | | | llvm-svn: 124526
* Revert r124518. It broke Linux self-host.Evan Cheng2011-01-291-6/+5
| | | | llvm-svn: 124522
* Re-commit r124462 with fixes. Tail recursion elim will now dup ret into ↵Evan Cheng2011-01-291-5/+6
| | | | | | unconditional predecessor to enable TCE on demand. llvm-svn: 124518
* Revert r124462. There are a few big regressions that I need to fix first.Evan Cheng2011-01-281-6/+5
| | | | llvm-svn: 124478
* Add a triple.Rafael Espindola2011-01-281-1/+1
| | | | llvm-svn: 124471
* Print the visibility of declarations.Rafael Espindola2011-01-281-0/+11
| | | | llvm-svn: 124468
* - Stop simplifycfg from duplicating "ret" instructions into unconditionalEvan Cheng2011-01-282-55/+6
| | | | | | | | branches. PR8575, rdar://5134905, rdar://8911460. - Allow codegen tail duplication to dup small return blocks after register allocation is done. llvm-svn: 124462
* Add a testcase for my last checkin.Eric Christopher2011-01-271-0/+21
| | | | llvm-svn: 124358
* Target/X86: Tweak win64's tailcall.NAKAMURA Takumi2011-01-262-6/+34
| | | | llvm-svn: 124272
* Fix whitespace.NAKAMURA Takumi2011-01-261-1/+0
| | | | llvm-svn: 124270
* Resolve DanglingDbgValue of PHI nodes where the use follows dbg.value ↵Devang Patel2011-01-251-1/+0
| | | | | | intrinisic. llvm-svn: 124203
* Don't merge restore with tail call instruction.Evan Cheng2011-01-251-0/+22
| | | | llvm-svn: 124167
* Speculatively revert r124138.Devang Patel2011-01-241-0/+1
| | | | llvm-svn: 124142
* Resolve DanglingDbgValue of PHI nodes where the use follows dbg.value ↵Devang Patel2011-01-241-0/+103
| | | | | | intrinisic. llvm-svn: 124138
* fix a missing shuffle pattern, PR9009. Patch by Artiom Myaskouvskey!Chris Lattner2011-01-241-0/+9
| | | | llvm-svn: 124102
* Pass sret arguments through the stack instead of through registers in Sparc ↵Venkatraman Govindaraju2011-01-221-0/+36
| | | | | | backend. It makes the code generated more compliant with the sparc32 ABI. llvm-svn: 124030
* Added ICC, FCC as uses of movcc instruction to generate correct code when ↵Venkatraman Govindaraju2011-01-221-22/+51
| | | | | | -mattr=v9 is used. llvm-svn: 124027
* Sparc backend: Venkatraman Govindaraju2011-01-211-16/+34
| | | | | | | Rename FLUSH to FLUSHW. Output "ta 3" instead of a "flushw" instruction if v8 instruction set is used. llvm-svn: 123997
* Last round of fixes for movw + movt global address codegen.Evan Cheng2011-01-216-39/+65
| | | | | | | | | | 1. Fixed ARM pc adjustment. 2. Fixed dynamic-no-pic codegen 3. CSE of pc-relative load of global addresses. It's now enabled by default for Darwin. llvm-svn: 123991
* Implement support for byval arguments in Sparc backend.Venkatraman Govindaraju2011-01-211-0/+18
| | | | llvm-svn: 123974
* Enable support for precise scheduling of the instruction selectionAndrew Trick2011-01-212-6/+11
| | | | | | | | | | | | | | | | | | | | | | | DAG. Disable using "-disable-sched-cycles". For ARM, this enables a framework for modeling the cpu pipeline and counting stalls. It also activates several heuristics to drive scheduling based on the model. Scheduling is inherently imprecise at this stage, and until spilling is improved it may defeat attempts to schedule. However, this framework provides greater control over tuning codegen. Although the flag is not target-specific, it should have very little affect on the default scheduler used by x86. The only two changes that affect x86 are: - scheduling a high-latency operation bumps the current cycle so independent operations can have their latency covered. i.e. two independent 4 cycle operations can produce results in 4 cycles, not 8 cycles. - Two operations with equal register pressure impact and no latency-based stalls on their uses will be prioritized by depth before height (height is irrelevant if no stalls occur in the schedule below this point). llvm-svn: 123971
* Convert -enable-sched-cycles and -enable-sched-hazard to -disableAndrew Trick2011-01-214-17/+17
| | | | | | | | | | | flags. They are still not enable in this revision. Added TargetInstrInfo::isZeroCost() to fix a fundamental problem with the scheduler's model of operand latency in the selection DAG. Generalized unit tests to work with sched-cycles. llvm-svn: 123969
* Don't be overly aggressive with CSE of "ldr constantpool". If it's a pc-relativeEvan Cheng2011-01-201-2/+6
| | | | | | | | | value, the "add pc" must be CSE'ed at the same time. We could follow the same approach as T2 by adding pseudo instructions that combine the ldr + "add pc". But the better approach is to use movw + movt (which I will enable soon), so I'll leave this as a TODO. llvm-svn: 123949
* Allow sign-extending of i8 and i16 to i128 on SPU. Kalle Raiskila2011-01-201-0/+21
| | | | llvm-svn: 123912
* Expand invalid return values for umulo and smulo. Handle these similarlyEric Christopher2011-01-201-0/+28
| | | | | | | | | | to add/sub by doing the normal operation and then checking for overflow afterwards. This generally relies on the DAG handling the later invalid operations as well. Fixes the 64-bit part of rdar://8622122 and rdar://8774702. llvm-svn: 123908
* Add test.Evan Cheng2011-01-201-0/+9
| | | | llvm-svn: 123906
* Sorry, several patches in one.Evan Cheng2011-01-201-10/+22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | TargetInstrInfo: Change produceSameValue() to take MachineRegisterInfo as an optional argument. When in SSA form, targets can use it to make more aggressive equality analysis. Machine LICM: 1. Eliminate isLoadFromConstantMemory, use MI.isInvariantLoad instead. 2. Fix a bug which prevent CSE of instructions which are not re-materializable. 3. Use improved form of produceSameValue. ARM: 1. Teach ARM produceSameValue to look pass some PIC labels. 2. Look for operands from different loads of different constant pool entries which have same values. 3. Re-implement PIC GA materialization using movw + movt. Combine the pair with a "add pc" or "ldr [pc]" to form pseudo instructions. This makes it possible to re-materialize the instruction, allow machine LICM to hoist the set of instructions out of the loop and make it possible to CSE them. It's a bit hacky, but it significantly improve code quality. 4. Some minor bug fixes as well. With the fixes, using movw + movt to materialize GAs significantly outperform the load from constantpool method. 186.crafty and 255.vortex improved > 20%, 254.gap and 176.gcc ~10%. llvm-svn: 123905
* Sparc backend: Implements a delay slot filler that attempt to fill delay slotsVenkatraman Govindaraju2011-01-201-0/+77
| | | | | | with useful instructions. llvm-svn: 123884
* If we can, lower the multiply part of a umulo/smulo call to a libcallEric Christopher2011-01-201-0/+14
| | | | | | | | | with an invalid type then split the result and perform the overflow check normally. Fixes the 32-bit parts of rdar://8622122 and rdar://8774702. llvm-svn: 123864
* Fix debug info for merged global.Devang Patel2011-01-201-0/+127
| | | | llvm-svn: 123862
* fix rdar://8878965, a regression I introduced with the recentChris Lattner2011-01-181-0/+32
| | | | | | llvm.objectsize changes. llvm-svn: 123771
* Add support for mips32 madd and msub instructions. Patch by Akira HatanakaBruno Cardoso Lopes2011-01-181-0/+65
| | | | llvm-svn: 123760
* Fix an off-by-one error in ctpop combining.Benjamin Kramer2011-01-171-2/+11
| | | | llvm-svn: 123664
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