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* Minor renaming of tests (for consistency with an in-development patch)Stephen Lin2013-04-201-10/+10
| | | | llvm-svn: 179954
* Don't litter .s files in test directory.Benjamin Kramer2013-04-201-1/+1
| | | | llvm-svn: 179937
* Add CodeGen support for functions that always return arguments via a new ↵Stephen Lin2013-04-202-0/+180
| | | | | | parameter attribute 'returned', which is taken advantage of in target-independent tail call opportunity detection and in ARM call lowering (when placed on an integral first parameter). llvm-svn: 179925
* Allow tail call opportunity detection through nested and/or multiple ↵Stephen Lin2013-04-201-0/+88
| | | | | | iterations of extractelement/insertelement indirection llvm-svn: 179924
* [mips] Instruction selection patterns for DSP-ASE vector shifts.Akira Hatanaka2013-04-191-0/+75
| | | | llvm-svn: 179906
* Fix PPC optimizeCompareInstr swapped-sub argument handlingHal Finkel2013-04-191-0/+42
| | | | | | | | | | | | | When matching a compare with a subtract where the arguments of the compare are swapped w.r.t. the arguments of the subtract, we need to negate the predicates (or CR bit indices) of the users. This, however, is not the same as inverting the predicate (negating LT -> GT, but inverting LT -> GE, for example). The ARM backend seems to do this correctly, but when I adapted the code for the PPC backend, I introduced an error in this logic. Comparison optimization is now enabled again by default. llvm-svn: 179899
* Do not mangle in MS-way the globals with magic \001 in the name.Anton Korobeynikov2013-04-192-8/+21
| | | | | | Based on the patch by David Nadlinger! llvm-svn: 179889
* Make test slightly more readable.Bill Wendling2013-04-191-4/+4
| | | | llvm-svn: 179888
* Add a testcase to make sure we generate the proper compact unwind section ↵Bill Wendling2013-04-191-0/+60
| | | | | | for a function that cannot produce a compact unwind encoding. llvm-svn: 179887
* Revert "PR14606: debug info imported_module support"Eric Christopher2013-04-1927-27/+27
| | | | | | This reverts commit r179836 as it seems to have caused test failures. llvm-svn: 179840
* PR14606: debug info imported_module supportDavid Blaikie2013-04-1927-27/+27
| | | | | | | | | | Adding another CU-wide list, in this case of imported_modules (since they should be relatively rare, it seemed better to add a list where each element had a "context" value, rather than add a (usually empty) list to every scope). This takes care of DW_TAG_imported_module, but to fully address PR14606 we'll need to expand this to cover DW_TAG_imported_declaration too. llvm-svn: 179836
* R600: Add pattern for the BFI_INT instructionTom Stellard2013-04-191-0/+34
| | | | llvm-svn: 179830
* R600: Reorganize lit tests and document how they should be organizedTom Stellard2013-04-1929-128/+174
| | | | llvm-svn: 179828
* Disable PPC comparison optimization by defaultHal Finkel2013-04-181-1/+1
| | | | | | | This seems to cause a stage-2 LLVM compile failure (by crashing TableGen); do I'm disabling this for now. llvm-svn: 179807
* Implement optimizeCompareInstr for PPCHal Finkel2013-04-181-0/+101
| | | | | | | | | | | | | | | Many PPC instructions have a so-called 'record form' which stores to a specific condition register the result of comparing the result of the instruction with zero (always as a signed comparison). For integer operations on PPC64, this is always a 64-bit comparison. This implementation is derived from the implementation in the ARM backend; there are some differences because PPC condition registers are allocatable virtual registers (although the record forms always use a specific one), and we look for a matching subtraction instruction after the compare (but before the first use) in addition to before it. llvm-svn: 179802
* X86: Add an SSE2 lowering for 64 bit compares when pcmpgtq (SSE4.2) isn't ↵Benjamin Kramer2013-04-181-0/+136
| | | | | | | | available. This pattern started popping up in vectorized min/max reductions. llvm-svn: 179797
* Allow misaligned stores in x86 fast-isel.Derek Schuff2013-04-181-0/+18
| | | | | | | | | | | | In X86FastISel::X86SelectStore(), improperly aligned stores are rejected and handled by the DAG-based ISel. However, X86FastISel::X86SelectLoad() makes no such requirement. There doesn't appear to be an x86 architectural correctness issue with allowing potentially unaligned store instructions. This patch removes this restriction. Patch by Jim Stichnot. llvm-svn: 179774
* Fix for PR14824, An ARM Load/Store Optimization bugHao Liu2013-04-181-0/+82
| | | | llvm-svn: 179751
* This patch teaches x86 fast-isel to generate the native div/idiv instructionsEli Bendersky2013-04-172-0/+163
| | | | | | | | | for the sdiv/srem/udiv/urem bitcode instructions. This is done for the i8, i16, and i32 types, as well as i64 for the x86_64 target. Patch by Jim Stichnoth llvm-svn: 179715
* R600: Make Export Instruction not duplicableVincent Lejeune2013-04-171-1/+3
| | | | llvm-svn: 179686
* [XCore] Extend test to check positve offsets are folded into addresses.Richard Osborne2013-04-161-7/+24
| | | | llvm-svn: 179621
* [XCore] Give test more generic name.Richard Osborne2013-04-161-0/+0
| | | | | | I intend to extend the test with more offset folding checks llvm-svn: 179620
* [XCore] Convert a couple of tests to FileCheck.Richard Osborne2013-04-162-17/+22
| | | | llvm-svn: 179619
* Implement ARM unwind opcode assembler.Logan Chien2013-04-165-13/+148
| | | | llvm-svn: 179591
* Add 64-bit multiply and divide instructions for SPARC v9.Jakob Stoklund Olesen2013-04-161-0/+21
| | | | llvm-svn: 179582
* R600/SI: Emit config values in register value pairs.Tom Stellard2013-04-151-3/+8
| | | | | | | | Instead of emitting config values in a predefined order, the code emitter will now emit a 32-bit register index followed by the 32-bit config value. llvm-svn: 179546
* R600/SI: Emit configuration value in the .AMDGPU.config ELF sectionTom Stellard2013-04-151-0/+1
| | | | llvm-svn: 179545
* R600: Emit ELF formatted code rather than raw ISA.Tom Stellard2013-04-151-0/+11
| | | | llvm-svn: 179544
* Avoid outputting temporary test file into source tree.Tim Northover2013-04-151-1/+1
| | | | llvm-svn: 179532
* Fix PPC64 CR spill location for callee-saved registersHal Finkel2013-04-151-19/+10
| | | | | | | | | | | | | | | | This fixes an ABI bug for non-Darwin PPC64. For the callee-saved condition registers, the spill location is specified relative to the stack pointer (SP + 8). However, this is not relative to the SP after the new stack frame is established, but instead relative to the caller's stack pointer (it is stored into the linkage area of the parent's stack frame). So, like with the link register, we don't directly spill the CRs with other callee-saved registers, but just mark them to be spilled during prologue generation. In practice, this reverts r179457 for PPC64 (but leaves it in place for PPC32). llvm-svn: 179500
* Use i32 for all SPARC shift amounts, even in 64-bit mode.Jakob Stoklund Olesen2013-04-141-0/+10
| | | | | | Test case by llvm-stress. llvm-svn: 179477
* Add support for the abs64 SPARC v9 code model.Jakob Stoklund Olesen2013-04-142-0/+20
| | | | | | For when 16 TB just isn't enough. llvm-svn: 179474
* Add support for the SPARC v9 abs44 code model.Jakob Stoklund Olesen2013-04-142-0/+16
| | | | | | | This is the default model for non-PIC 64-bit code. It supports text+data+bss linked anywhere in the low 16 TB of the address space. llvm-svn: 179473
* Also put target flags on SPARC constant pool references.Jakob Stoklund Olesen2013-04-141-0/+30
| | | | | | | Constant pool entries are accessed exactly the same way as global variables. llvm-svn: 179471
* Fix patterns for 64-bit pointers.Jakob Stoklund Olesen2013-04-141-0/+9
| | | | | | This fixes the pic32 code model for SPARC v9. llvm-svn: 179469
* Define SPARC code models.Jakob Stoklund Olesen2013-04-131-0/+23
| | | | | | | Currently, only abs32 and pic32 are implemented. Add a test case for abs32 with 64-bit code. 64-bit PIC code is currently broken. llvm-svn: 179463
* Spill and restore PPC CR registers using the FP when we have oneHal Finkel2013-04-131-1/+14
| | | | | | | | | | For functions that need to spill CRs, and have dynamic stack allocations, the value of the SP during the restore is not what it was during the save, and so we need to use the FP in these cases (as for all of the other spills and restores, but the CR restore has a special code path because its reserved slot, like the link register, is specified directly relative to the adjusted SP). llvm-svn: 179457
* Further generalize this scheduler test.Andrew Trick2013-04-131-2/+2
| | | | | | The order of copies depends on queue order, which is not very stable. llvm-svn: 179456
* Fix a dislexic regex.Andrew Trick2013-04-131-1/+1
| | | | llvm-svn: 179455
* Add a missing REQUIRES: assertsAndrew Trick2013-04-131-0/+1
| | | | llvm-svn: 179453
* MI-Sched: schedule physreg copies.Andrew Trick2013-04-131-0/+48
| | | | | | | | | | | The register allocator expects minimal physreg live ranges. Schedule physreg copies accordingly. This is slightly tricky when they occur in the middle of the scheduling region. For now, this is handled by rescheduling the copy when its associated instruction is scheduled. Eventually we may instead bundle them, but only if we can preserve the bundles as parallel copies during regalloc. llvm-svn: 179449
* [mips] Reapply r179420 and r179421.Akira Hatanaka2013-04-131-7/+106
| | | | llvm-svn: 179434
* Revert r179420 and r179421.Akira Hatanaka2013-04-121-106/+7
| | | | llvm-svn: 179422
* [mips] Instruction selection patterns for carry-setting and using addAkira Hatanaka2013-04-121-0/+11
| | | | | | instructions. llvm-svn: 179421
* [mips] v4i8 and v2i16 add, sub and mul instruction selection patterns.Akira Hatanaka2013-04-121-7/+95
| | | | llvm-svn: 179420
* Replace coff-/elf-dump with llvm-readobjNico Rieck2013-04-1215-365/+231
| | | | llvm-svn: 179361
* Fix the test on linux by setting the triple and the align formatNadav Rotem2013-04-121-4/+4
| | | | llvm-svn: 179354
* Add a flag to align all basic blocks in the function.Nadav Rotem2013-04-121-0/+22
| | | | | | | | | | When debugging performance regressions we often ask ourselves if the regression that we see is due to poor isel/sched/ra or due to some micro-architetural problem. When comparing two code sequences one good way to rule out front-end bottlenecks (and other the issues) is to force code alignment. This pass adds a flag that forces the alignment of all of the basic blocks in the program. llvm-svn: 179353
* Use FileCheck instead of grep.Preston Gurd2013-04-112-17/+12
| | | | llvm-svn: 179322
* Mips specific inline asm memory operand modifier test caseJack Carter2013-04-111-0/+16
| | | | | | These changes are based on commit responses for r179135. llvm-svn: 179315
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