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* Mark the return address stack slot as mutable when moving the return addressArnold Schwaighofer2010-02-221-0/+55
| | | | | | | | | | | | | | | | | during a tail call. A parameter might overwrite this stack slot during the tail call. The sequence during a tail call is: 1.) load return address to temp reg 2.) move parameters (might involve storing to return address stack slot) 3.) store return address to new location from temp reg If the stack location is marked immutable CodeGen can colocate load (1) with the store (3). This fixes bug 6225. llvm-svn: 96783
* Remove the logic for reasoning about NaNs from the code that formsDan Gohman2010-02-221-44/+168
| | | | | | | | | | SSE min and max instructions. The real thing this code needs to be concerned about is negative zero. Update the sse-minmax.ll test accordingly, and add tests for -enable-unsafe-fp-math mode as well. llvm-svn: 96775
* When emitting an instruction which depends on both a post-incrementedDan Gohman2010-02-221-0/+32
| | | | | | | | | induction variable value and a loop-variant value, don't force the insert position to be at the post-increment position, because it may not be dominated by the loop-variant value. This fixes a use-before-def problem noticed on PPC. llvm-svn: 96774
* add some no-unwinds, other minor cleanups.Chris Lattner2010-02-213-30/+30
| | | | llvm-svn: 96756
* add a triple so that this doesn't fail due to linux/ppc register printing Chris Lattner2010-02-211-1/+1
| | | | | | syntax. llvm-svn: 96748
* filecheckize and add nouwinds.Chris Lattner2010-02-211-9/+16
| | | | llvm-svn: 96745
* IT turns out that during jumpless setcc lowering eq and ne were swapped.Anton Korobeynikov2010-02-211-22/+22
| | | | | | This fixes PR6348 llvm-svn: 96734
* fix and un-xfail X86/vec_ss_load_fold.llChris Lattner2010-02-211-1/+0
| | | | llvm-svn: 96720
* temporarily disable this.Chris Lattner2010-02-211-1/+2
| | | | llvm-svn: 96717
* Check for overflow when scaling up an add or an addrec forDan Gohman2010-02-191-0/+37
| | | | | | scaled reuse. llvm-svn: 96692
* Add support for the 'alignstack' attribute to the x86 backend. Fixes PR5254.Charles Davis2010-02-191-1/+18
| | | | | | Also, FileCheck'ize a test. llvm-svn: 96686
* Revert commits 96556 and 96640, because commit 96556 breaks theDuncan Sands2010-02-194-46/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | dragonegg self-host build. I reverted 96640 in order to revert 96556 (96640 goes on top of 96556), but it also looks like with both of them applied the breakage happens even earlier. The symptom of the 96556 miscompile is the following crash: llvm[3]: Compiling AlphaISelLowering.cpp for Release build cc1plus: /home/duncan/tmp/tmp/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:4982: void llvm::SelectionDAG::ReplaceAllUsesWith(llvm::SDNode*, llvm::SDNode*, llvm::SelectionDAG::DAGUpdateListener*): Assertion `(!From->hasAnyUseOfValue(i) || From->getValueType(i) == To->getValueType(i)) && "Cannot use this version of ReplaceAllUsesWith!"' failed. Stack dump: 0. Running pass 'X86 DAG->DAG Instruction Selection' on function '@_ZN4llvm19AlphaTargetLowering14LowerOperationENS_7SDValueERNS_12SelectionDAGE' g++: Internal error: Aborted (program cc1plus) This occurs when building LLVM using LLVM built by LLVM (via dragonegg). Probably LLVM has miscompiled itself, though it may have miscompiled GCC and/or dragonegg itself: at this point of the self-host build, all of GCC, LLVM and dragonegg were built using LLVM. Unfortunately this kind of thing is extremely hard to debug, and while I did rummage around a bit I didn't find any smoking guns, aka obviously miscompiled code. Found by bisection. r96556 | evancheng | 2010-02-18 03:13:50 +0100 (Thu, 18 Feb 2010) | 5 lines Some dag combiner goodness: Transform br (xor (x, y)) -> br (x != y) Transform br (xor (xor (x,y), 1)) -> br (x == y) Also normalize (and (X, 1) == / != 1 -> (and (X, 1)) != / == 0 to match to "test on x86" and "tst on arm" r96640 | evancheng | 2010-02-19 01:34:39 +0100 (Fri, 19 Feb 2010) | 16 lines Transform (xor (setcc), (setcc)) == / != 1 to (xor (setcc), (setcc)) != / == 1. e.g. On x86_64 %0 = icmp eq i32 %x, 0 %1 = icmp eq i32 %y, 0 %2 = xor i1 %1, %0 br i1 %2, label %bb, label %return => testl %edi, %edi sete %al testl %esi, %esi sete %cl cmpb %al, %cl je LBB1_2 llvm-svn: 96672
* Transform (xor (setcc), (setcc)) == / != 1 toEvan Cheng2010-02-191-0/+31
| | | | | | | | | | | | | | | | | | | (xor (setcc), (setcc)) != / == 1. e.g. On x86_64 %0 = icmp eq i32 %x, 0 %1 = icmp eq i32 %y, 0 %2 = xor i1 %1, %0 br i1 %2, label %bb, label %return => testl %edi, %edi sete %al testl %esi, %esi sete %cl cmpb %al, %cl je LBB1_2 llvm-svn: 96640
* When determining the set of interesting reuse factors, considerDan Gohman2010-02-191-1/+57
| | | | | | | | strides in foreign loops. This helps locate reuse opportunities with existing induction variables in foreign loops and reduces the need for inserting new ones. This fixes rdar://7657764. llvm-svn: 96629
* getSplatIndex assumes that the first element of the mask contains the splat ↵Mon P Wang2010-02-181-5/+12
| | | | | | | | | index which is not always true if the mask contains undefs. Modified it to return the first non undef value. llvm-svn: 96621
* Always normalize spill weights, also for intervals created by spilling.Jakob Stoklund Olesen2010-02-182-2/+6
| | | | | | | | | | | | | | Moderate the weight given to very small intervals. The spill weight given to new intervals created when spilling was not normalized in the same way as the original spill weights calculated by CalcSpillWeights. That meant that restored registers would tend to hang around because they had a much higher spill weight that unspilled registers. This improves the runtime of a few tests by up to 10%, and there are no significant regressions. llvm-svn: 96613
* Make CodePlacementOpt detect special EH control flow byDan Gohman2010-02-181-0/+45
| | | | | | | | | | checking whether AnalyzeBranch disagrees with the CFG directly, rather than looking for EH_LABEL instructions. EH_LABEL instructions aren't always at the end of the block, due to FP_REG_KILL and other things. This fixes an infinite loop compiling MultiSource/Benchmarks/Bullet. llvm-svn: 96611
* remove empty fileChris Lattner2010-02-181-0/+0
| | | | llvm-svn: 96573
* Use NEON vmin/vmax instructions for floating-point selects.Bob Wilson2010-02-181-0/+65
| | | | | | Radar 7461718. llvm-svn: 96572
* Some dag combiner goodness:Evan Cheng2010-02-184-67/+15
| | | | | | | | Transform br (xor (x, y)) -> br (x != y) Transform br (xor (xor (x,y), 1)) -> br (x == y) Also normalize (and (X, 1) == / != 1 -> (and (X, 1)) != / == 0 to match to "test on x86" and "tst on arm" llvm-svn: 96556
* Don't check for comments, which vary between subtargets.Dan Gohman2010-02-171-1/+1
| | | | llvm-svn: 96434
* Don't attempt to divide INT_MIN by -1; consider such cases toDan Gohman2010-02-171-0/+26
| | | | | | have overflowed. llvm-svn: 96428
* roundss is an sse 4 thing, fix the test on non-sse41 buildersChris Lattner2010-02-171-1/+1
| | | | | | like llvm-gcc-x86_64-darwin10-selfhost llvm-svn: 96417
* Make g5 target explicit; scheduling affects register choice.Dale Johannesen2010-02-161-1/+1
| | | | llvm-svn: 96413
* fix rdar://7653908, a crash on a case where we would fold a loadChris Lattner2010-02-161-0/+25
| | | | | | | | | | into a roundss intrinsic, producing a cyclic dag. The root cause of this is badness handling ComplexPattern nodes in the old dagisel that I noticed through inspection. Eliminate a copy of the of the code that handled ComplexPatterns by making EmitChildMatchCode call into EmitMatchCode. llvm-svn: 96408
* Adjust register numbers in tests to compensate for theDale Johannesen2010-02-164-14/+14
| | | | | | new lack of R2. llvm-svn: 96407
* filecheckizeChris Lattner2010-02-161-3/+9
| | | | llvm-svn: 96404
* Look for SSE and instructions of this form: (and x, (build_vector c1,c2,c3,c4)).Evan Cheng2010-02-162-4/+12
| | | | | | | | | | | | | If there exists a use of a build_vector that's the bitwise complement of the mask, then transform the node to (and (xor x, (build_vector -1,-1,-1,-1)), (build_vector ~c1,~c2,~c3,~c4)). Since this transformation is only useful when 1) the given build_vector will become a load from constpool, and 2) (and (xor x -1), y) matches to a single instruction, I decided this is appropriate as a x86 specific transformation. rdar://7323335 llvm-svn: 96389
* Add support for emitting non-temporal stores for DAGs markedDavid Greene2010-02-161-0/+22
| | | | | | | | | | non-temporal. Fix from r96241 for botched encoding of MOVNTDQ. Add documentation for !nontemporal metadata. Add a simpler movnt testcase. llvm-svn: 96386
* Fix pr6111: Avoid using the LR register for the target address of an indirectBob Wilson2010-02-161-0/+14
| | | | | | | | branch in ARM v4 code, since it gets clobbered by the return address before it is used. Instead of adding a new register class containing all the GPRs except LR, just use the existing tGPR class. llvm-svn: 96360
* Split the main for-each-use loop again, this time for GenerateTruncates,Dan Gohman2010-02-161-0/+59
| | | | | | | as it also peeks at which registers are being used by other uses. This makes LSR less sensitive to use-list order. llvm-svn: 96308
* Preliminary patch to improve dwarf EH generation - Hooks to return ↵Anton Korobeynikov2010-02-151-1/+1
| | | | | | Personality / FDE / LSDA / TType encoding depending on target / options (e.g. code model / relocation model) - MCIzation of Dwarf EH printer to use encoding information - Stub generation for ELF target (needed for indirect references) - Some other small changes here and there llvm-svn: 96285
* Fix PR6300.Jakob Stoklund Olesen2010-02-151-0/+80
| | | | | | | A virtual register can be used before it is defined in the same MBB if the MBB is part of a loop. Teach the implicit-def pass about this case. llvm-svn: 96279
* Last week we were generating code with duplicate induction variables in thisBob Wilson2010-02-151-0/+4
| | | | | | | test, but the problem seems to have gone away today. Add a check to make sure it doesn't come back. llvm-svn: 96277
* remove empty file.Chris Lattner2010-02-151-0/+0
| | | | llvm-svn: 96271
* revert r96241. It breaks two regression tests, isn't documented,Chris Lattner2010-02-151-84/+0
| | | | | | and the testcase needs improvement. llvm-svn: 96265
* fix PR6305 by handling BlockAddress in a helper functionChris Lattner2010-02-151-3/+7
| | | | | | called by jump threading. llvm-svn: 96263
* Add support for emitting non-temporal stores for DAGs markedDavid Greene2010-02-151-0/+84
| | | | | | non-temporal. llvm-svn: 96241
* Fix PR6283.Jakob Stoklund Olesen2010-02-131-0/+260
| | | | | | | | | | | When coalescing with a physreg, remember to add imp-def and imp-kill when dealing with sub-registers. Also fix a related bug in VirtRegRewriter where substitutePhysReg may reallocate the operand list on an instruction and invalidate the reg_iterator. This can happen when a register is mentioned twice on the same instruction. llvm-svn: 96072
* Besides removing phi cycles that reduce to a single value, also remove deadBob Wilson2010-02-134-4/+42
| | | | | | | | phi cycles. Adjust a few tests to keep dead instructions from being optimized away. This (together with my previous change for phi cycles) fixes Apple radar 7627077. llvm-svn: 96057
* When save/restoring CR at prolog/epilog, in a largeDale Johannesen2010-02-121-0/+30
| | | | | | | | | | | | | | | | | stack frame, the prolog/epilog code was using the same register for the copy of CR and the address of the save slot. Oops. This is fixed here for Darwin, sort of, by reserving R2 for this case. A better way would be to do the store before the decrement of SP, which is safe on Darwin due to the red zone. SVR4 probably has the same problem, but I don't know how to fix it; there is no red zone and R2 is already used for something else. I'm going to leave it to someone interested in that target. Better still would be to rewrite the CR-saving code completely; spilling each CR subregister individually is horrible code. llvm-svn: 96015
* Testcases for recent stdcall / fastcall mangling improvementsAnton Korobeynikov2010-02-122-0/+28
| | | | llvm-svn: 95982
* Cleanup stdcall / fastcall name mangling.Anton Korobeynikov2010-02-121-2/+2
| | | | | | This should fix alot of problems we saw so far, e.g. PRs 5851 & 2936 llvm-svn: 95980
* Reapply the new LoopStrengthReduction code, with compile time andDan Gohman2010-02-1217-51/+500
| | | | | | | | | | bug fixes, and with improved heuristics for analyzing foreign-loop addrecs. This change also flattens IVUsers, eliminating the stride-oriented groupings, which makes it easier to work with. llvm-svn: 95975
* Add a new pass on machine instructions to optimize away PHI cycles that Bob Wilson2010-02-121-0/+34
| | | | | | | | | | | reduce down to a single value. InstCombine already does this transformation but DAG legalization may introduce new opportunities. This has turned out to be important for ARM where 64-bit values are split up during type legalization: InstCombine is not able to remove the PHI cycles on the 64-bit values but the separate 32-bit values can be optimized. I measured the compile time impact of this (running llc on 176.gcc) and it was not significant. llvm-svn: 95951
* Reapply coalescer fix for better cross-class coalescing.Jakob Stoklund Olesen2010-02-116-9/+7
| | | | | | This time with fixed test cases. llvm-svn: 95938
* The previous fix of widening divides that trap was too fragile as it depends ↵Mon P Wang2010-02-101-0/+29
| | | | | | | | | | | on custom lowering and requires that certain types exist in ValueTypes.h. Modified widening to check if an op can trap and if so, the widening algorithm will apply only the op on the defined elements. It is safer to do this in widening because the optimizer can't guarantee removing unused ops in some cases. llvm-svn: 95823
* Delete dead PHI machine instructions. These can be created due to typeBob Wilson2010-02-102-4/+6
| | | | | | | | | legalization even when the IR-level optimizer has removed dead phis, such as when the high half of an i64 value is unused on a 32-bit target. I had to adjust a few test cases that had dead phis. This is a partial fix for Radar 7627077. llvm-svn: 95816
* Now that ShrinkDemandedOps() is separated out from DAG combine. It sometimes ↵Evan Cheng2010-02-101-0/+13
| | | | | | leave some obvious nops which dag combine used to clean up afterwards e.g. (trunk (ext n)) -> n. Look for them and squash them. llvm-svn: 95757
* move tests that depend on the x86 backend out of codegen/generic,Chris Lattner2010-02-0910-202/+1
| | | | | | and remove a few old and unreduced ones. Fixes PR5624. llvm-svn: 95656
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