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* ARM: locate user-defined text sections next to default text.Jim Grosbach2012-10-041-0/+21
| | | | | | | | | | | | Make sure functions located in user specified text sections (via the section attribute) are located together with the default text sections. Otherwise, for large object files, the relocations for call instructions are more likely to be out of range. This becomes even more likely in the presence of LTO. rdar://12402636 llvm-svn: 165254
* [ms-inline asm] Add support in the X86AsmPrinter for printing memory referencesChad Rosier2012-10-031-0/+14
| | | | | | | | | | | in the Intel syntax. The MC layer supports emitting in the Intel syntax, but this would require the inline assembly MachineInstr to be lowered to an MCInst before emission. This is potential future work, but for now emitting directly from the MachineInstr suffices. llvm-svn: 165173
* Fix a cycle in the DAG. In this code we replace multiple loads with a single ↵Nadav Rotem2012-10-031-0/+31
| | | | | | | | | | | load and multiple stores with a single load. We create the wide loads and stores (and their chains) before we remove the scalar loads and stores and fix the DAG chain. We attempted to merge loads with a different chain. When that happened, the assumption that it is safe to RAUW broke and a cycle was introduced. llvm-svn: 165148
* A DAGCombine optimization for mergeing consecutive stores to memory. The ↵Nadav Rotem2012-10-031-0/+273
| | | | | | | | | | | | | | | | | | | | | optimization is not profitable in many cases because modern processors perform multiple stores in parallel and merging stores prior to merging requires extra work. We handle two main cases: 1. Store of multiple consecutive constants: q->a = 3; q->4 = 5; In this case we store a single legal wide integer. 2. Store of multiple consecutive loads: int a = p->a; int b = p->b; q->a = a; q->b = b; In this case we load/store either ilegal vector registers or legal wide integer registers. llvm-svn: 165125
* Fixed a bug in the ExecutionDependencyFix pass that caused dependencies to ↵Silviu Baranga2012-10-031-0/+22
| | | | | | not propagate through implicit defs. llvm-svn: 165102
* The early if conversion pass is ready to be used as an opt-in.Jakob Stoklund Olesen2012-10-031-1/+1
| | | | | | | | | | | Enable the pass by default for targets that request it, and change the -enable-early-ifcvt to the opposite -disable-early-ifcvt. There are still some x86 regressions when enabling early if-conversion because of the missing machine models. Disable the pass for x86 until machine models are added. llvm-svn: 165075
* Fix a serious X86 instruction selection bug. InEvan Cheng2012-10-021-0/+16
| | | | | | | | | | | | | X86DAGToDAGISel::PreprocessISelDAG(), isel is moving load inside callseq_start / callseq_end so it can be folded into a call. This can create a cycle in the DAG when the call is glued to a copytoreg. We have been lucky this hasn't caused too many issues because the pre-ra scheduler has special handling of call sequences. However, it has caused a crash in a specific tailcall case. rdar://12393897 llvm-svn: 165072
* Make sure to put our sret argument into %rax on x86-64. Fixes PR13563!Nick Lewycky2012-10-021-0/+13
| | | | llvm-svn: 165063
* Make sure the whole live range is covered when values are pruned twice.Jakob Stoklund Olesen2012-10-021-1/+26
| | | | | | | | | | | | | | | | | | | | | | | | JoinVals::pruneValues() calls LIS->pruneValue() to avoid conflicts when overlapping two different values. This produces a set of live range end points that are used to reconstruct the live range (with SSA update) after joining the two registers. When a value is pruned twice, the set of end points was insufficient: v1 = DEF v1 = REPLACE1 v1 = REPLACE2 KILL v1 The end point at KILL would only reconstruct the live range from REPLACE2 to KILL, leaving the range REPLACE1-REPLACE2 dead. Add REPLACE2 as an end point in this case so the full live range is reconstructed. This fixes PR13999. llvm-svn: 165056
* Fix broken tests.Benjamin Kramer2012-10-022-3/+3
| | | | llvm-svn: 165019
* Fix PR13991: legalizing an overflowing multiplication operation is harder thanDuncan Sands2012-10-021-0/+14
| | | | | | | the add/sub case since in the case of multiplication you also have to check that the operation in the larger type did not overflow. llvm-svn: 165017
* test/CodeGen/X86/red-zone2.ll: Add -mtriple=x86_64-linux, and FileCheck-ize.NAKAMURA Takumi2012-10-011-3/+4
| | | | llvm-svn: 164975
* checking test case for r164811. was an omission to not check this in. this ↵Reed Kotler2012-10-011-0/+41
| | | | | | was already approved llvm-svn: 164972
* Fix PR13899Michael Liao2012-10-011-0/+58
| | | | | | | | | - Update maximal stack alignment when stack arguments are prepared before a call. - Test cases are enhanced to show it's not a Win32 specific issue but a generic one. llvm-svn: 164946
* Revert r164910 because it causes failures to several phase2 builds.Nadav Rotem2012-09-304-158/+12
| | | | llvm-svn: 164911
* A DAGCombine optimization for merging consecutive stores. This optimization ↵Nadav Rotem2012-09-304-12/+158
| | | | | | | | | | | | | | | | | | | is not profitable in many cases because moden processos can store multiple values in parallel, and preparing the consecutive store requires some work. We only handle these cases: 1. Consecutive stores where the values and consecutive loads. For example: int a = p->a; int b = p->b; q->a = a; q->b = b; 2. Consecutive stores where the values are constants. Foe example: q->a = 4; q->b = 5; llvm-svn: 164910
* Add LLVM support for Swift.Bob Wilson2012-09-2926-35/+224
| | | | llvm-svn: 164899
* Whitespace.Bob Wilson2012-09-291-2/+2
| | | | llvm-svn: 164898
* Speculatively revert commit 164885 (nadav) in the hope of ressurecting a pile ofDuncan Sands2012-09-294-158/+12
| | | | | | | | | | | | | | | | | | | | buildbots. Original commit message: A DAGCombine optimization for merging consecutive stores. This optimization is not profitable in many cases because moden processos can store multiple values in parallel, and preparing the consecutive store requires some work. We only handle these cases: 1. Consecutive stores where the values and consecutive loads. For example: int a = p->a; int b = p->b; q->a = a; q->b = b; 2. Consecutive stores where the values are constants. Foe example: q->a = 4; q->b = 5; llvm-svn: 164890
* A DAGCombine optimization for merging consecutive stores. This optimization ↵Nadav Rotem2012-09-294-12/+158
| | | | | | | | | | | | | | | | | | | is not profitable in many cases because moden processos can store multiple values in parallel, and preparing the consecutive store requires some work. We only handle these cases: 1. Consecutive stores where the values and consecutive loads. For example: int a = p->a; int b = p->b; q->a = a; q->b = b; 2. Consecutive stores where the values are constants. Foe example: q->a = 4; q->b = 5; llvm-svn: 164885
* Do not delete BBs if their addresses are taken. rdar://12396696Evan Cheng2012-09-281-0/+53
| | | | llvm-svn: 164866
* MIPS DSP: add operands to make sure instruction strings are being matched.Akira Hatanaka2012-09-282-23/+23
| | | | llvm-svn: 164849
* MIPS DSP: other miscellaneous instructions.Akira Hatanaka2012-09-282-0/+71
| | | | llvm-svn: 164845
* Testcase for r164835Manman Ren2012-09-281-0/+28
| | | | llvm-svn: 164842
* MIPS DSP: ADDUH.QB instruction sub-class.Akira Hatanaka2012-09-281-0/+200
| | | | llvm-svn: 164840
* Enable the new coalescer algorithm by default.Jakob Stoklund Olesen2012-09-271-1/+0
| | | | | | | The new coalescer is better at merging values into unused vector lanes, improving NEON code. llvm-svn: 164794
* MIPS DSP: ABSQ_S.PH instruction sub-class.Akira Hatanaka2012-09-272-0/+215
| | | | llvm-svn: 164787
* MIPS DSP: SHLL.QB instruction sub-class.Akira Hatanaka2012-09-272-0/+252
| | | | llvm-svn: 164786
* Avoid dereferencing a NULL pointer.Jakob Stoklund Olesen2012-09-271-0/+35
| | | | | | Fixes PR13943. llvm-svn: 164778
* [arm-fast-isel] Add support for ELF PIC.Jush Lu2012-09-271-0/+18
| | | | | | | This is a preliminary step towards ELF support; currently ARMFastISel hasn't been used for ELF object files yet. llvm-svn: 164759
* Test case for r164755 and 164756.Akira Hatanaka2012-09-272-0/+294
| | | | llvm-svn: 164757
* MIPS DSP: ADDU.QB instruction sub-class.Akira Hatanaka2012-09-272-0/+309
| | | | llvm-svn: 164754
* MIPS DSP: Branch on Greater Than or Equal To Value 32 in DSPControl Pos ↵Akira Hatanaka2012-09-271-0/+10
| | | | | | Field instruction. llvm-svn: 164751
* MIPS DSP: all the remaining instructions which read or write accumulators.Akira Hatanaka2012-09-272-0/+348
| | | | llvm-svn: 164750
* MIPS DSP: add support for extract-word instructions.Akira Hatanaka2012-09-271-0/+110
| | | | llvm-svn: 164749
* MIPS DSP: add vector load/store patterns.Akira Hatanaka2012-09-271-0/+27
| | | | llvm-svn: 164744
* ARM/atomicrmw_minmax.ll: Fix RUN line.NAKAMURA Takumi2012-09-261-1/+1
| | | | llvm-svn: 164687
* Fix ordering of operands on lowering of atomicrmw min/max nodes on ARM.James Molloy2012-09-261-0/+21
| | | | llvm-svn: 164685
* llvm/test/CodeGen/X86/mulx*.ll: Fix copypasto.NAKAMURA Takumi2012-09-262-2/+2
| | | | llvm-svn: 164681
* Add SARX/SHRX/SHLX code generation supportMichael Liao2012-09-263-2/+180
| | | | llvm-svn: 164675
* Add RORX code generation supportMichael Liao2012-09-264-5/+59
| | | | llvm-svn: 164674
* Add MULX code generation supportMichael Liao2012-09-262-0/+44
| | | | llvm-svn: 164673
* Generate an error message instead of asserting or segfaulting when we have aBill Wendling2012-09-261-0/+11
| | | | | | | | scalar-to-vector conversion that we cannot handle. For instance, when an invalid constraint is used in an inline asm statement. <rdar://problem/12284092> llvm-svn: 164662
* Generate an error message instead of asserting or segfaulting when we have aBill Wendling2012-09-261-0/+11
| | | | | | | | scalar-to-vector conversion that we cannot handle. For instance, when an invalid constraint is used in an inline asm statement. <rdar://problem/12284092> llvm-svn: 164657
* Add missing i64 max/min/umax/umin on 32-bit targetMichael Liao2012-09-252-1/+51
| | | | | | - Turn on atomic6432.ll and add specific test case as well llvm-svn: 164616
* Fix an illegal tailcall opt where the callee returns a double via xmm while ↵Evan Cheng2012-09-251-3/+26
| | | | | | caller returns x86_fp80 via st0. rdar://12229511 llvm-svn: 164588
* Mark jump tables in code sections with DataRegion directives.Jim Grosbach2012-09-241-0/+12
| | | | | | | | | Even out-of-line jump tables can be in the code section, so mark them as data-regions for those targets which support the directives. rdar://12362871&12362974 llvm-svn: 164571
* Specify MachinePointerInfo as refering to the argument value and offset of theRoman Divacky2012-09-241-0/+27
| | | | | | | store when handling byval arguments. Thus preventing reordering of the store with load with post-RA scheduler. llvm-svn: 164553
* Revise test to avoid using of 'grep'Michael Liao2012-09-231-20/+14
| | | | llvm-svn: 164472
* Enhance test case of atomic16 to verify inst encoding fixed in r164453.Michael Liao2012-09-221-0/+6
| | | | llvm-svn: 164465
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