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* Remove regression that requires post-RA scheduling from a target that does ↵David Goodwin2009-09-301-33/+0
| | | | | | not use that scheduler. llvm-svn: 83128
* Remove -post-RA-schedule flag and add a TargetSubtarget method to enable ↵David Goodwin2009-09-305-5/+5
| | | | | | post-register-allocation scheduling. By default it is off. For ARM, enable/disable with -mattr=+/-postrasched. Enable by default for cortex-a8. llvm-svn: 83122
* Post-RA regressions.David Goodwin2009-09-295-4/+113
| | | | llvm-svn: 83075
* Fix PR4687. Pre ARMv5te does not support ldrd / strd. Patch by John Tytgat.Evan Cheng2009-09-291-0/+19
| | | | llvm-svn: 83058
* Add a CHECK line to check the position of the second divsd.Dan Gohman2009-09-281-0/+1
| | | | llvm-svn: 83009
* Make ARM and Thumb2 32-bit immediate materialization into a single 32-bit pseudoEvan Cheng2009-09-281-6/+26
| | | | | | | | | instruction. This makes it re-materializable. Thumb2 will split it back out into two instructions so IT pass will generate the right mask. Also, this expose opportunies to optimize the movw to a 16-bit move. llvm-svn: 82982
* Coalescer should not delete extract_subreg, insert_subreg, and subreg_to_reg ofEvan Cheng2009-09-283-2/+25
| | | | | | | | | | | physical registers. This is especially critical for the later two since they start the live interval of a super-register. e.g. %DO<def> = INSERT_SUBREG %D0<undef>, %S0<kill>, 1 If this instruction is eliminated, the register scavenger will not be happy as D0 is not defined previously. This fixes PR5055. llvm-svn: 82968
* Use movt/movw pair to materialize 32 bit constants on ARMv6T2+.Anton Korobeynikov2009-09-271-0/+9
| | | | | | This should be better than single load from constpool. llvm-svn: 82948
* Enable pre-regalloc load / store multiple pass for Thumb2.Evan Cheng2009-09-271-0/+12
| | | | llvm-svn: 82893
* implement and document support for filecheck variables. ThisChris Lattner2009-09-271-16/+16
| | | | | | | | | | allows matching and remembering a string and then matching and verifying that the string occurs later in the file. Change X86/xor.ll to use this in some cases where the test was checking for an arbitrary register allocation decision. llvm-svn: 82891
* Remove this test.Evan Cheng2009-09-261-58/+0
| | | | llvm-svn: 82869
* Convert comparisons like (x == infinity) to (x >= infinity) on targetsDan Gohman2009-09-261-0/+76
| | | | | | where FCMP_OEQ is not legal and FCMP_OGE is, such as x86. llvm-svn: 82861
* "Update" tests for -disable-if-conversion removal. I think branch.ll should justDaniel Dunbar2009-09-262-1/+2
| | | | | | be removed, but I XFAIL'd it for now. llvm-svn: 82847
* Convert test to filecheck.Evan Cheng2009-09-261-3/+11
| | | | llvm-svn: 82835
* Unbreak MachineLICM for instructions that reference RIP on x86-64 too.Dan Gohman2009-09-252-18/+42
| | | | llvm-svn: 82825
* Fix MachineSink to be able to sink instructions that use physical registersDan Gohman2009-09-251-0/+18
| | | | | | | | which have no defs anywhere in the function. In particular, this fixes sinking of instructions that reference RIP on x86-64, which is currently being modeled as a register. llvm-svn: 82815
* Flip -disable-post-RA-scheduler to -post-RA-scheduler.Evan Cheng2009-09-255-6/+6
| | | | llvm-svn: 82803
* Improve MachineMemOperand handling.Dan Gohman2009-09-251-1/+1
| | | | | | | | | | | | | | | | | | | | | - Allocate MachineMemOperands and MachineMemOperand lists in MachineFunctions. This eliminates MachineInstr's std::list member and allows the data to be created by isel and live for the remainder of codegen, avoiding a lot of copying and unnecessary translation. This also shrinks MemSDNode. - Delete MemOperandSDNode. Introduce MachineSDNode which has dedicated fields for MachineMemOperands. - Change MemSDNode to have a MachineMemOperand member instead of its own fields with the same information. This introduces some redundancy, but it's more consistent with what MachineInstr will eventually want. - Ignore alignment when searching for redundant loads for CSE, but remember the greatest alignment. Target-specific code which previously used MemOperandSDNodes with generic SDNodes now use MemIntrinsicSDNodes, with opcodes in a designated range so that the SelectionDAG framework knows that MachineMemOperand information is available. llvm-svn: 82794
* Add readonly to some sin and cos calls; transformationsDale Johannesen2009-09-252-13/+13
| | | | | | being checked aren't valid without it. llvm-svn: 82786
* reimplement the regex matching strategy by building a singleChris Lattner2009-09-251-8/+8
| | | | | | | | | | | | | | | | | regex and matching it instead of trying to match chunks at a time. Matching chunks at a time broke with check lines like CHECK: foo {{.*}}bar because the .* would eat the entire rest of the line and bar would never match. Now we just escape the fixed strings for the user, so that something like: CHECK: a() {{.*}}??? is matched as: CHECK: {{a\(\) .*\?\?\?}} transparently "under the covers". llvm-svn: 82779
* pr4926: ARM requires the stack pointer to be aligned, even for leaf functions.Bob Wilson2009-09-251-0/+17
| | | | | | | | | | | | | | | | | | | | For the AAPCS ABI, SP must always be 4-byte aligned, and at any "public interface" it must be 8-byte aligned. For the older ARM APCS ABI, the stack alignment is just always 4 bytes. For X86, we currently align SP at entry to a function (e.g., to 16 bytes for Darwin), but no stack alignment is needed at other times, such as for a leaf function. After discussing this with Dan, I decided to go with the approach of adding a new "TransientStackAlignment" field to TargetFrameInfo. This value specifies the stack alignment that must be maintained even in between calls. It defaults to 1 except for ARM, where it is 4. (Some other targets may also want to set this if they have similar stack requirements. It's not currently required for PPC because it sets targetHandlesStackFrameRounding and handles the alignment in target-specific code.) The existing StackAlignment value specifies the alignment upon entry to a function, which is how we've been using it anyway. llvm-svn: 82767
* convert testcases to filecheck.Chris Lattner2009-09-252-18/+66
| | | | llvm-svn: 82759
* remove a large unreduced testcaseChris Lattner2009-09-251-85/+0
| | | | llvm-svn: 82756
* Convert to FileCheck.Bob Wilson2009-09-241-4/+6
| | | | llvm-svn: 82710
* Add nounwind to this test.Dan Gohman2009-09-241-1/+1
| | | | llvm-svn: 82708
* Fix PR5024 with a big hammer: disable the double-def assertion in the scavenger.Evan Cheng2009-09-241-0/+21
| | | | | | | | | | | | | | | | | | | | | | LiveVariables add implicit kills to correctly track partial register kills. This works well enough and is fairly accurate. But coalescer can make it impossible to maintain these markers. e.g. BL <ga:sss1>, %R0<kill,undef>, %S0<kill>, %R0<imp-def>, %R1<imp-def,dead>, %R2<imp-def,dead>, %R3<imp-def,dead>, %R12<imp-def,dead>, %LR<imp-def,dead>, %D0<imp-def>, ... ... %reg1031<def> = FLDS <cp#1>, 0, 14, %reg0, Mem:LD4[ConstantPool] ... %S0<def> = FCPYS %reg1031<kill>, 14, %reg0, %D0<imp-use,kill> When reg1031 and S0 are coalesced, the copy (FCPYS) will be eliminated the the implicit-kill of D0 is lost. In this case it's possible to move the marker to the FLDS. But in many cases, this is not possible. Suppose %reg1031<def> = FOO <cp#1>, %D0<imp-def> ... %S0<def> = FCPYS %reg1031<kill>, 14, %reg0, %D0<imp-use,kill> When FCPYS goes away, the definition of S0 is the "FOO" instruction. However, transferring the D0 implicit-kill to FOO doesn't work since it is the def of D0 itself. We need to fix this in another time by introducing a "kill" pseudo instruction to track liveness. Disabling the assertion is not ideal, but machine verifier is doing that job now. It's important to know double-def is not a miscomputation since it means a register should be free but it's not tracked as free. It's a performance issue instead. llvm-svn: 82677
* Clean up LiveVariables and change how it deals with partial updates and ↵Evan Cheng2009-09-242-1/+92
| | | | | | kills. This also eliminate the horrible check which scan forward to the end of the basic block. It should be faster and more accurate. llvm-svn: 82676
* Add nounwind.Evan Cheng2009-09-231-1/+1
| | | | llvm-svn: 82637
* Fix PR5024. LiveVariables physical register defs should *commit* only after allEvan Cheng2009-09-231-0/+23
| | | | | | | | of the defs are processed. Also fix a implicit_def propagation bug: a implicit_def of a physical register should be applied to uses of the sub-registers. llvm-svn: 82616
* Fix a obvious logic error.Evan Cheng2009-09-231-0/+124
| | | | llvm-svn: 82610
* Fix PR5024. LiveVariables::FindLastPartialDef should return a set of ↵Evan Cheng2009-09-221-0/+14
| | | | | | sub-registers that were defined by the last partial def, not just a single sub-register. llvm-svn: 82535
* Fix a pasto. Also simplify for Bill's benefit.Evan Cheng2009-09-222-2/+2
| | | | llvm-svn: 82505
* Clean up spill weight computation. Also some changes to give loop inductionEvan Cheng2009-09-217-8/+44
| | | | | | | | | | variable increment / decrement slighter high priority. This has major impact on some micro-benchmarks. On MultiSource/Applications and spec tests, it's a minor win. It also reduce 256.bzip instruction count by 8%, 55 on 164.gzip on i386 / Darwin. llvm-svn: 82485
* Add a comment mentioning the rdar number associated with this test.Dan Gohman2009-09-211-0/+1
| | | | llvm-svn: 82471
* Add support for rematerializing FsFLD0SS and FsFLD0SD as constant-poolDan Gohman2009-09-211-0/+95
| | | | | | loads in order to reduce register pressure. llvm-svn: 82470
* Recognize SSE min and max opportunities in even more cases.Dan Gohman2009-09-212-4/+323
| | | | | | | | | | And fix a bug with the behavior of min/max instructions formed from fcmp uge comparisons. Also, use FiniteOnlyFPMath() for this code instead of UnsafeFPMath, as it is more specific. llvm-svn: 82466
* Fix PR4986. "r1024 = insert_subreg r1024, undef, 2" cannot be turned in an ↵Evan Cheng2009-09-211-0/+34
| | | | | | implicit_def. Instead, it's an identity copy so it should be eliminated. Also make sure to update livevariable kill information. llvm-svn: 82436
* When computing live intervals for earlyclobber operands,Dale Johannesen2009-09-201-0/+15
| | | | | | | | | | we pushed the beginning of the interval back 1, so the interval would overlap with inputs that die. We were also pushing the end of the interval back 1, though, which means the earlyclobber didn't overlap with other output operands. Don't do this. PR 4964. llvm-svn: 82342
* Fix PR4926. When target hook EmitInstrWithCustomInserter() insert new basic ↵Evan Cheng2009-09-191-0/+30
| | | | | | blocks and update CFG, it should also inform sdisel of the changes so the phi source operands will come from the right basic blocks. llvm-svn: 82311
* Delete the label names from this test to make it less fragile.Dan Gohman2009-09-181-4/+4
| | | | llvm-svn: 82276
* Make a new X8632_MachoTargetObjectFile TLOF implementation whose Chris Lattner2009-09-181-3/+4
| | | | | | | | | | | | | | | | | | | | | | getSymbolForDwarfGlobalReference is smart enough to know that it needs to register the stub it references with MachineModuleInfoMachO, so that it gets emitted at the end of the file. Move stub emission from X86ATTAsmPrinter::doFinalization to the new X86ATTAsmPrinter::EmitEndOfAsmFile asmprinter hook. The important thing here is that EmitEndOfAsmFile is called *after* the ehframes are emitted, so we get all the stubs. This allows us to remove a gross hack from the asmprinter where it would "just know" that it needed to output stubs for personality functions. Now this is all driven from a consistent interface. The testcase change is just reordering the expected output now that the stubs come out after the ehframe instead of before. This also unblocks other changes that Bill wants to make. llvm-svn: 82269
* Model the carry bit on ppc32. Without this we couldDale Johannesen2009-09-181-0/+62
| | | | | | | move a SUBFC (etc.) below the SUBFE (etc.) that consumed the carry bit. Add missing ADDIC8, noticed along the way. llvm-svn: 82266
* Add support for using the FLAGS result of or, xor, and and instructionsDan Gohman2009-09-183-4/+91
| | | | | | | on x86, to avoid explicit test instructions. A few existing tests changed due to arbitrary register allocation differences. llvm-svn: 82263
* Allow symbols to start from the digit if target requests it. This allows, ↵Anton Korobeynikov2009-09-181-0/+22
| | | | | | | | | e.g. pinning variables to specified absolute address. Make use of this feature for MSP430. This unbreaks PR4776. llvm-svn: 82227
* make this testcase check darwin32 alsoChris Lattner2009-09-171-0/+8
| | | | llvm-svn: 82182
* rename testChris Lattner2009-09-171-0/+0
| | | | llvm-svn: 82181
* convert to filecheckChris Lattner2009-09-171-1/+4
| | | | llvm-svn: 82179
* rename fileChris Lattner2009-09-171-0/+0
| | | | llvm-svn: 82178
* Remove test cases using -regalloc=simple.Daniel Dunbar2009-09-172-22/+0
| | | | llvm-svn: 82130
* Fix PR4910: Broken logic in coalescer means when a physical register ↵Evan Cheng2009-09-171-0/+64
| | | | | | liveness is being shortened, the sub-registers were not. The symptom is the register allocator could not find a free register for this particular test. llvm-svn: 82108
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