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* Fix miscompile due to StackColoring incorrectly merging stack slots (PR15707)Derek Schuff2013-05-151-0/+22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | IR optimisation passes can result in a basic block that contains: llvm.lifetime.start(%buf) ... llvm.lifetime.end(%buf) ... llvm.lifetime.start(%buf) Before this change, calculateLiveIntervals() was ignoring the second lifetime.start() and was regarding %buf as being dead from the lifetime.end() through to the end of the basic block. This can cause StackColoring to incorrectly merge %buf with another stack slot. Fix by removing the incorrect Starts[pos].isValid() and Finishes[pos].isValid() checks. Just doing: Starts[pos] = Indexes->getMBBStartIdx(MBB); Finishes[pos] = Indexes->getMBBEndIdx(MBB); unconditionally would be enough to fix the bug, but it causes some test failures due to stack slots not being merged when they were before. So, in order to keep the existing tests passing, treat LiveIn and LiveOut separately rather than approximating the live ranges by merging LiveIn and LiveOut. This fixes PR15707. Patch by Mark Seaborn. llvm-svn: 181922
* [SystemZ] Make use of SUBTRACT HALFWORDRichard Sandiford2013-05-151-0/+131
| | | | | | Thanks to Ulrich Weigand for noticing that this instruction was missing. llvm-svn: 181893
* ARM ISel: Don't create illegal types during LowerMULArnold Schwaighofer2013-05-141-0/+24
| | | | | | | | | | | | | | | | | The transformation happening here is that we want to turn a "mul(ext(X), ext(X))" into a "vmull(X, X)", stripping off the extension. We have to make sure that X still has a valid vector type - possibly recreate an extension to a smaller type. In case of a extload of a memory type smaller than 64 bit we used create a ext(load()). The problem with doing this - instead of recreating an extload - is that an illegal type is exposed. This patch fixes this by creating extloads instead of ext(load()) sequences. Fixes PR15970. radar://13871383 llvm-svn: 181842
* Hexagon: Pass to replace tranfer/copy instructions into combine instructionJyotsna Verma2013-05-142-6/+38
| | | | | | where possible. llvm-svn: 181817
* Reapply "Subtract isn't commutative, fix this for MMX psub." withEric Christopher2013-05-141-0/+213
| | | | | | | a somewhat randomly chosen cpu that will minimize cpu specific differences on bots. llvm-svn: 181814
* Temporarily revert "Subtract isn't commutative, fix this for MMX psub."Eric Christopher2013-05-141-213/+0
| | | | | | It's causing failures on the atom bot. llvm-svn: 181812
* Subtract isn't commutative, fix this for MMX psub.Eric Christopher2013-05-141-0/+213
| | | | | | Patch by Andrea DiBiagio. llvm-svn: 181809
* Recognize sparc64 as an alias for sparcv9 triples.Jakob Stoklund Olesen2013-05-141-2/+2
| | | | | | Patch by Brad Smith! llvm-svn: 181808
* Hexagon: Add patterns to generate 'combine' instructions.Jyotsna Verma2013-05-141-0/+80
| | | | llvm-svn: 181805
* Hexagon: ArePredicatesComplement should not restrict itself to TFRs.Jyotsna Verma2013-05-141-0/+32
| | | | llvm-svn: 181803
* Fix ARM FastISel tests, as a first step to enabling ARM FastISelDerek Schuff2013-05-1417-162/+135
| | | | | | | | | | | | | | | | | | | | | ARM FastISel is currently only enabled for iOS non-Thumb1, and I'm working on enabling it for other targets. As a first step I've fixed some of the tests. Changes to ARM FastISel tests: - Different triples don't generate the same relocations (especially movw/movt versus constant pool loads). Use a regex to allow either. - Mangling is different. Use a regex to allow either. - The reserved registers are sometimes different, so registers get allocated in a different order. Capture the names only where this occurs. - Add -verify-machineinstrs to some tests where it works. It doesn't work everywhere it should yet. - Add -fast-isel-abort to many tests that didn't have it before. - Split out the VarArg test from fast-isel-call.ll into its own test. This simplifies test setup because of --check-prefix. Patch by JF Bastien llvm-svn: 181801
* PPC32: Fix stack collision between FP and CR save areas.Bill Schmidt2013-05-141-4/+8
| | | | | | | | | | | | | | | | | The changes to CR spill handling missed a case for 32-bit PowerPC. The code in PPCFrameLowering::processFunctionBeforeFrameFinalized() checks whether CR spill has occurred using a flag in the function info. This flag is only set by storeRegToStackSlot and loadRegFromStackSlot. spillCalleeSavedRegisters does not call storeRegToStackSlot, but instead produces MI directly. Thus we don't see the CR is spilled when assigning frame offsets, and the CR spill ends up colliding with some other location (generally the FP slot). This patch sets the flag in spillCalleeSavedRegisters for PPC32 so that the CR spill is properly detected and gets its own slot in the stack frame. llvm-svn: 181800
* Hexagon: Test case to check if branch probabilities are properly reflected inJyotsna Verma2013-05-141-0/+79
| | | | | | the jump instructions in the form of taken/not-taken hint. llvm-svn: 181799
* R600/SI: Add lit test coverage for the remaining patterns added recentlyMichel Danzer2013-05-146-11/+111
| | | | | Reviewed-by: Christian König <christian.koenig@amd.com> llvm-svn: 181775
* This is the first of three patches which creates stubs used forReed Kotler2013-05-141-0/+1028
| | | | | | | | | | | | | | | | | | | | | | | Mips16/32 floating point interoperability. When Mips16 code calls external functions that would normally have some of its parameters or return values passed in floating point registers, it needs (Mips32) helper functions to do this because while in Mips16 mode there is no ability to access the floating point registers. In Pic mode, this is done with a set of predefined functions in libc. This case is already handled in llvm for Mips16. In static relocation mode, for efficiency reasons, the compiler generates stubs that the linker will use if it turns out that the external function is a Mips32 function. (If it's Mips16, then it does not need the helper stubs). These stubs are identically named and the linker knows about these tricks and will not create multiple copies and will delete them if they are not needed. llvm-svn: 181753
* StackColoring: don't clear an instruction's mem operand if the underlyingAkira Hatanaka2013-05-141-0/+39
| | | | | | | object is a PseudoSourceValue and PseudoSourceValue::isConstant returns true (i.e., points to memory that has a constant value). llvm-svn: 181751
* PPC64: Constant initializers with dynamic relocations go in .data.rel.ro.Bill Schmidt2013-05-131-0/+27
| | | | | | | | | | | | | | | | | | | | | This fixes warning messages observed in the oggenc application test in projects/test-suite. Special handling is needed for the 64-bit PowerPC SVR4 ABI when a constant is initialized with a pointer to a function in a shared library. Because a function address is implemented as the address of a function descriptor, the use of copy relocations can lead to problems with initialization. GNU ld therefore replaces copy relocations with dynamic relocations to be resolved by the dynamic linker. This means the constant cannot reside in the read-only data section, but instead belongs in .data.rel.ro, which is designed for constants containing dynamic relocations. The implementation creates a class PPC64LinuxTargetObjectFile inheriting from TargetLoweringObjectFileELF, which behaves like its parent except to place constants of this sort into .data.rel.ro. The test case is reduced from the oggenc application. llvm-svn: 181723
* [mips] Add option -mno-ldc1-sdc1.Akira Hatanaka2013-05-131-0/+45
| | | | | | | | This option is used when the user wants to avoid emitting double precision FP loads and stores. Double precision FP loads and stores are expanded to single precision instructions after register allocation. llvm-svn: 181718
* Correctly preserve the input chain for potential tailcall nodes whoseLang Hames2013-05-131-0/+17
| | | | | | | | | | | | return values are bitcasts. The chain had previously been being clobbered with the entry node to the dag, which sometimes caused other code in the function to be erroneously deleted when tailcall optimization kicked in. <rdar://problem/13827621> llvm-svn: 181696
* Fix PR15950 A bug in DAG Combiner about undef maskHao Liu2013-05-131-0/+10
| | | | llvm-svn: 181682
* Add -mtriple=mipsel-linux-gnu to the test so that the compiler doesReed Kotler2013-05-111-4/+4
| | | | | | not think it can support small data sections. llvm-svn: 181654
* Checkin in of first of several patches to finish implementation ofReed Kotler2013-05-101-0/+77
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | mips16/mips32 floating point interoperability. This patch fixes returns from mips16 functions so that if the function was in fact called by a mips32 hard float routine, then values that would have been returned in floating point registers are so returned. Mips16 mode has no floating point instructions so there is no way to load values into floating point registers. This is needed when returning float, double, single complex, double complex in the Mips ABI. Helper functions in libc for mips16 are available to do this. For efficiency purposes, these helper functions have a different calling convention from normal Mips calls. Registers v0,v1,a0,a1 are used to pass parameters instead of a0,a1,a2,a3. This is because v0,v1,a0,a1 are the natural registers used to return floating point values in soft float. These values can then be moved to the appropriate floating point registers with no extra cost. The only register that is modified is ra in this call. The helper functions make sure that the return values are in the floating point registers that they would be in if soft float was not in effect (which it is for mips16, though the soft float is implemented using a mips32 library that uses hard float). llvm-svn: 181641
* Hexagon: Fix switch cases in HexagonVLIWPacketizer.cpp.Jyotsna Verma2013-05-101-0/+28
| | | | llvm-svn: 181624
* DAGCombiner: Generate a correct constant for vector types when folding (xor ↵Benjamin Kramer2013-05-101-0/+11
| | | | | | | | (and)) into (and (not)). PR15948. llvm-svn: 181597
* R600: Remove AMDILPeeopholeOptimizer and replace optimizations with tablegen ↵Tom Stellard2013-05-101-0/+26
| | | | | | | | | | | | | | patterns The BFE optimization was the only one we were actually using, and it was emitting an intrinsic that we don't support. https://bugs.freedesktop.org/show_bug.cgi?id=64201 Reviewed-by: Christian König <christian.koenig@amd.com> NOTE: This is a candidate for the 3.3 branch. llvm-svn: 181580
* R600: Expand SUB for v2i32/v4i32Tom Stellard2013-05-101-0/+15
| | | | | | | | | | Patch by: Aaron Watry Reviewed-by: Tom Stellard <thomas.stellard@amd.com> Signed-off-by: Aaron Watry <awatry@gmail.com> NOTE: This is a candidate for the 3.3 branch. llvm-svn: 181579
* R600: Expand MUL for v4i32/v2i32Tom Stellard2013-05-101-0/+16
| | | | | | | | | | | | Fixes piglit test for OpenCL builtin mul24, and allows mad24 to run. Patch by: Aaron Watry Reviewed-by: Tom Stellard <thomas.stellard@amd.com> Signed-off-by: Aaron Watry <awatry@gmail.com> NOTE: This is a candidate for the 3.3 branch. llvm-svn: 181578
* R600: Expand SRA for v4i32/v2i32Tom Stellard2013-05-101-0/+13
| | | | | | | | | | | | v2: Add v4i32 test Patch by: Aaron Watry Reviewed-by: Tom Stellard <thomas.stellard@amd.com> Signed-off-by: Aaron Watry <awatry@gmail.com> NOTE: This is a candidate for the 3.3 branch. llvm-svn: 181577
* R600: Expand vselect for v4i32 and v2i32Tom Stellard2013-05-101-0/+17
| | | | | | | | | | | | v2: Add vselect v4i32 test Patch by: Aaron Watry Reviewed-by: Tom Stellard <thomas.stellard@amd.com> Signed-off-by: Aaron Watry <awatry@gmail.com> NOTE: This is a candidate for the 3.3 branch. llvm-svn: 181576
* Teach SelectionDAG to constant fold all-constant FMA nodes the same way that ↵Owen Anderson2013-05-091-0/+8
| | | | | | it constant folds FADD, FMUL, etc. llvm-svn: 181555
* Generate a compact unwind encoding in the face of a stack alignment push.Bill Wendling2013-05-091-0/+30
| | | | | | | | | | | | | We generate a `push' of a random register (%rax) if the stack needs to be aligned by the size of that register. However, this could mess up compact unwind generation. In particular, we want to still generate compact unwind in the presence of this monstrosity. Check if the push of of the %rax/%eax register. If it is and it's marked with the `FrameSetup' flag, then we can generate a compact unwind encoding for the function only if the push is the last FrameSetup instruction. llvm-svn: 181540
* Hexagon: Use relation map for getMatchingCondBranchOpcode() and Jyotsna Verma2013-05-091-0/+30
| | | | | | getInvertedPredicatedOpcode() functions instead of switch cases. llvm-svn: 181530
* [XCore] Fix handling of functions where only the LR is spilled.Richard Osborne2013-05-091-0/+11
| | | | | | | | | | | | | | Previously we only checked if the LR required saving if the frame size was non zero. However because the caller reserves 1 word for the callee to use that doesn't count towards our frame size it is possible for the LR to need saving and for the frame size to be 0. We didn't hit when the LR needed saving because of a function calls because the 1 word of stack we must allocate for our callee means the frame size is always non zero in this case. However we can hit this case if the LR is clobbered in inline asm. llvm-svn: 181520
* [mips] Add instruction selection pattern for (seteq $LHS, 0).Akira Hatanaka2013-05-081-0/+11
| | | | llvm-svn: 181459
* Fix handling of anonymous aggregate parameters for powerpc*-apple-darwin8.Bill Schmidt2013-05-081-0/+90
| | | | | | | | This fixes bug 15821 similarly to the powerpc64-linux fix for bug 14779. Patch by David Fang. llvm-svn: 181449
* R600/SI: Add lit tests for llvm.SI.imageload and llvm.SI.resinfo intrinsicsMichel Danzer2013-05-082-0/+197
| | | | | | | Adapted from the llvm.SI.sample test. Reviewed-by: Christian König <christian.koenig@amd.com> llvm-svn: 181425
* PPCInstrInfo::optimizeCompareInstr should not optimize FP comparesHal Finkel2013-05-081-2/+2
| | | | | | | | The floating-point record forms on PPC don't set the condition register bits based on a comparison with zero (like the integer record forms do), but rather based on the exception status bits. llvm-svn: 181423
* Fix a bug in codegenprep where it was losing track of values OptimizeMemoryInstNick Lewycky2013-05-081-0/+44
| | | | | | by switching to a ValueMap. Patch by Andrea DiBiagio! llvm-svn: 181397
* DAGCombiner: Simplify inverted bit testsDavid Majnemer2013-05-082-10/+20
| | | | | | | | Fold (xor (and x, y), y) -> (and (not x), y) This removes an opportunity for a constant to appear twice. llvm-svn: 181395
* Hexagon: Fix Small Data support to handle -G 0 correctly.Jyotsna Verma2013-05-071-0/+26
| | | | llvm-svn: 181344
* Reverting r181331.Jyotsna Verma2013-05-071-26/+0
| | | | | | Missing file, HexagonSplitConst32AndConst64.cpp, from lib/Target/Hexagon/CMakeLists.txt. llvm-svn: 181334
* Hexagon: Fix Small Data support to handle -G 0 correctly.Jyotsna Verma2013-05-071-0/+26
| | | | llvm-svn: 181331
* Reduce attributes.Bill Wendling2013-05-061-2/+2
| | | | llvm-svn: 181245
* R600: Emit config values in register / value pairsTom Stellard2013-05-061-2/+3
| | | | | | Reviewed-by: Vincent Lejeune <vljn@ovi.com> Tested-By: Aaron Watry <awatry@gmail.com> llvm-svn: 181228
* R600: Stop emitting the instruction type byte before each instructionTom Stellard2013-05-062-4/+4
| | | | | | Reviewed-by: Vincent Lejeune <vljn@ovi.com> Tested-By: Aaron Watry <awatry@gmail.com> llvm-svn: 181225
* R600: Emit ISA for CALL_FS_* instructionsTom Stellard2013-05-061-0/+15
| | | | | | Reviewed-by: Vincent Lejeune <vljn@ovi.com> Tested-By: Aaron Watry <awatry@gmail.com> llvm-svn: 181223
* [SystemZ] Add CodeGen test casesUlrich Weigand2013-05-06296-0/+31125
| | | | | | | | | | | This adds all CodeGen tests for the SystemZ target. This version of the patch incorporates feedback from a review by Sean Silva. Thanks to all reviewers! Patch by Richard Sandiford. llvm-svn: 181204
* Fix slightly too aggressive conact_vector optimization.Michael Kuperstein2013-05-061-0/+14
| | | | | | (Would sometimes optimize away conacts used to extend a vector with undef values) llvm-svn: 181186
* Add a testcase that checks that we generate functions with frameBill Wendling2013-05-061-0/+32
| | | | | | pointers or not depending upon the function attributes. llvm-svn: 181180
* Test case for r181160 and r181161. rdar://13782395Evan Cheng2013-05-051-0/+71
| | | | llvm-svn: 181162
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