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* [DebugInfo] Add DILabel metadata and intrinsic llvm.dbg.label.Shiva Chen2018-05-0937-67/+67
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In order to set breakpoints on labels and list source code around labels, we need collect debug information for labels, i.e., label name, the function label belong, line number in the file, and the address label located. In order to keep these information in LLVM IR and to allow backend to generate debug information correctly. We create a new kind of metadata for labels, DILabel. The format of DILabel is !DILabel(scope: !1, name: "foo", file: !2, line: 3) We hope to keep debug information as much as possible even the code is optimized. So, we create a new kind of intrinsic for label metadata to avoid the metadata is eliminated with basic block. The intrinsic will keep existing if we keep it from optimized out. The format of the intrinsic is llvm.dbg.label(metadata !1) It has only one argument, that is the DILabel metadata. The intrinsic will follow the label immediately. Backend could get the label metadata through the intrinsic's parameter. We also create DIBuilder API for labels to be used by Frontend. Frontend could use createLabel() to allocate DILabel objects, and use insertLabel() to insert llvm.dbg.label intrinsic in LLVM IR. Differential Revision: https://reviews.llvm.org/D45024 Patch by Hsiangkai Wang. llvm-svn: 331841
* Revert "[X86][CET] Shadow stack fix for setjmp/longjmp"Jessica Paquette2018-05-081-133/+0
| | | | | | | | | | | | This reverts commit 30962eca38ef02666ebcdded72a94f2cd0292d68. This commit has been causing test asan failures on a build bot. http://green.lab.llvm.org/green/job/clang-stage1-configure-RA/45108/ Original commit: https://reviews.llvm.org/D46181 llvm-svn: 331813
* Changing constants in a test (NFC)Daniel Neilson2018-05-081-36/+39
| | | | | | | | | Summary: Changing the lengths of the atomic memory intrinsics in a test to make sure that they don't get lowered into loads/stores if/when expansion of these occurs in selectiondag. llvm-svn: 331800
* [CodeGenPrepare] Move Extension Instructions Through Logical And Shift ↵Guozhi Wei2018-05-083-20/+3
| | | | | | | | | | Instructions CodeGenPrepare pass move extension instructions close to load instructions in different BB, so they can be combined later. But the extension instructions can't move through logical and shift instructions in current implementation. This patch enables this enhancement, so we can eliminate more extension instructions. Differential Revision: https://reviews.llvm.org/D45537 llvm-svn: 331783
* [X86] Split off WriteIMul64 from WriteIMul schedule class (PR36931)Simon Pilgrim2018-05-082-31/+31
| | | | | | | This fixes a couple of BtVer2 missing instructions that weren't been handled in the override. NOTE: There are still a lot of overrides that still need cleaning up! llvm-svn: 331770
* [X86] Split WriteIDiv into div/idiv 8/16/32/64 implementations (PR36930)Simon Pilgrim2018-05-081-14/+14
| | | | | | | I've created the necessary classes but there are still a lot of overrides that need cleaning up. NOTE: The Znver1 model was missing some div/idiv variants in the instregex patterns and wasn't setting the resource cycles at all in the overrides. llvm-svn: 331767
* [X86] Add vector masked load/store scheduler classes (PR32857)Simon Pilgrim2018-05-081-8/+8
| | | | | | Split off from existing vector load/store classes to remove InstRW overrides. llvm-svn: 331760
* [X86] Mark all byval parameters as aliasedJeremy Morse2018-05-081-5/+1
| | | | | | | | | | | | | | | This is a fix for PR30290: by marking all byval stack slots as being aliased, the instruction scheduler is more conservative about rescheduling memory accesses to such stack slots as an LLVM Value* might alias it. This fixes errors such as in the patched test case, where reads and writes to a data structure are illegally mixed. This could be fixed better in the future with better analysis for the instruction scheduler to know what Values alias what stack slots. Differential Revision: https://reviews.llvm.org/D45022 llvm-svn: 331749
* [X86][CET] Shadow stack fix for setjmp/longjmpAlexander Ivchenko2018-05-081-0/+133
| | | | | | | | | | | | This patch adds a shadow stack fix when compiling setjmp/longjmp with the shadow stack enabled. This allows setjmp/longjmp to work correctly with CET. Patch by mike.dvoretsky Differential Revision: https://reviews.llvm.org/D46181 llvm-svn: 331748
* [MachineVerifier][GlobalISel] Verifying generic extends and truncatesRoman Tereshin2018-05-081-0/+87
| | | | | | | | | | | | | | | | | Making sure we don't truncate / extend pointers, don't try to change vector topology or bitcast vectors to scalars or back, and most importantly, don't extend to a smaller type or truncate to a large one. Reviewers: qcolombet t.p.northover aditya_nandakumar Reviewed By: qcolombet Subscribers: rovka, kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D46490 llvm-svn: 331718
* Follow Up on [MachineVerifier][GlobalISel] NFC, Improving MO printing and ↵Roman Tereshin2018-05-071-10/+2
| | | | | | | | refactoring visitMachineInstrBefore Fixing accidentally broken CodeGen/X86/verifier-generic-types-1.mir test llvm-svn: 331695
* [MachineVerifier][GlobalISel] Checking that generic instrs have LLTs on all ↵Roman Tereshin2018-05-072-4/+28
| | | | | | | | | | | | | | | | | | | | | | | | | | vregs Every generic machine instruction must have generic virtual registers only, that is, have a low-level type attached to each operand. Previously MachineVerifier would catch a type missing on an operand only if the previous operand for the the same type index exists and have a type attached to it and it will report it as a type mismatch. This is incosistent behaviour and a misleading error message. This commit makes sure MachineVerifier explicitly checks that the types are there for every operand and if not provides a straightforward error message. Reviewers: qcolombet t.p.northover bogner ab Reviewed By: qcolombet Subscribers: rovka, kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D46455 llvm-svn: 331694
* [MachineVerifier][GlobalISel] NFC, Improving MO printing and refactoring ↵Roman Tereshin2018-05-072-0/+34
| | | | | | | | | | | | | | | | | | | | visitMachineInstrBefore This is an NFC pre-commit for the following "Checking that generic instrs have LLTs on all vregs" commit. This overloads MachineOperand::print to make it possible to print LLTs with standalone machine operands. This also overloads MachineVerifier::print(...MachineOperand...) with an optional LLT using the newly introduced MachineOperand::print variant; no actual calls added. This also refactors MachineVerifier::visitMachineInstrBefore in the parts dealing with all generic instructions (checking Selected property, LLTs, and phys regs). llvm-svn: 331693
* [DAGCombiner] Masked merge: enhance handling of 'andn' with immediatesRoman Lebedev2018-05-071-7/+7
| | | | | | | | | | | | | | | | | | | | | Summary: Split off from D46031. The previous patch, D46493, completely disabled unfolding in case of immediates. But we can do better: {F6120274} {F6120277} https://rise4fun.com/Alive/xJS Reviewers: spatel, craig.topper Reviewed By: spatel Subscribers: andreadb, llvm-commits Differential Revision: https://reviews.llvm.org/D46494 llvm-svn: 331685
* [DagCombiner] Not all 'andn''s work with immediates.Roman Lebedev2018-05-073-17/+16
| | | | | | | | | | | | | | | | | | | | | | | | | Summary: Split off from D46031. In masked merge case, this degrades IPC by decreasing instruction count. {F6108777} The next patch should be able to recover and improve this. This also affects the transform @spatel have added in D27489 / rL289738, and the test coverage for X86 was missing. But after i have added it, and looked at the changes in MCA, i'm somewhat confused. {F6093591} {F6093592} {F6093593} I'd say this regression is an improvement, since `IPC` increased in that case? Reviewers: spatel, craig.topper Reviewed By: spatel Subscribers: andreadb, llvm-commits, spatel Differential Revision: https://reviews.llvm.org/D46493 llvm-svn: 331684
* [X86] Split WriteFAdd/WriteFCmp/WriteFMul schedule classesSimon Pilgrim2018-05-071-1/+1
| | | | | | | | Split to support single/double for scalar, XMM and YMM/ZMM instructions - removing InstrRW overrides for these instructions. Fixes Atom ADDSUBPD instruction and reclassifies VFPCLASS as WriteFCmp which is closer in behaviour. llvm-svn: 331672
* [X86][AVX2] Tag VPMOVSX/VPMOVZX ymm instructions as WriteShuffle256Simon Pilgrim2018-05-072-22/+22
| | | | | | | | These are more like cross-lane shuffles than regular shuffles - we already do this for AVX512 equivalents. Differential Revision: https://reviews.llvm.org/D46229 llvm-svn: 331659
* [DAGCombine][NFC] Masked merge unfolding: comment: some tests are non-canonicalRoman Lebedev2018-05-071-0/+8
| | | | | | As requested in https://reviews.llvm.org/D46494#inline-407282 llvm-svn: 331650
* [X86][Znver1] Remove WriteFMul/WriteFRcp InstRW overrides/aliases.Simon Pilgrim2018-05-071-8/+8
| | | | | | Fixes x87 schedules to more closely match Agner - AMD doesn't tend to "special case" x87 instructions as much as Intel. llvm-svn: 331645
* [X86] Split WriteFDiv schedule classes to support single/double scalar, XMM ↵Simon Pilgrim2018-05-073-30/+30
| | | | | | | | and YMM/ZMM instructions. This removes all InstrRW overrides for these instructions - some x87 overrides remain but most use default (and realistic) values. llvm-svn: 331643
* Add option -verify-cfiinstrs to run verifier in CFIInstrInserterPetar Jovanovic2018-05-072-0/+52
| | | | | | | | | Instead of enabling it for non NDEBUG builds, use -verify-cfiinstrs to run verifier in CFIInstrInserter. It defaults to false. Differential Revision: https://reviews.llvm.org/D46444 llvm-svn: 331635
* [X86] Split WriteFRcp/WriteFRsqrt/WriteFSqrt schedule classesSimon Pilgrim2018-05-077-35/+35
| | | | | | | | | | | | | WriteFRcp/WriteFRsqrt are split to support scalar, XMM and YMM/ZMM instructions. WriteFSqrt is split into single/double/long-double sizes and scalar, XMM, YMM and ZMM instructions. This removes all InstrRW overrides for these instructions. NOTE: There were a couple of typos in the Znver1 model - notably a 1cy throughput for SQRT that is highly unlikely and doesn't tally with Agner. NOTE: I had to add Agner's numbers for several targets for WriteFSqrt80. llvm-svn: 331629
* [X86] Enable reciprocal estimates for v16f32 vectors by using ↵Craig Topper2018-05-063-31/+61
| | | | | | | | | | | | | | | | | | | VRCP14PS/VRSQRT14PS Summary: The legacy VRCPPS/VRSQRTPS instructions aren't available in 512-bit versions. The new increased precision versions are. So we can use those to implement v16f32 reciprocal estimates. For KNL CPUs we can probably use VRCP28PS/VRSQRT28PS and avoid the NR step altogether, but I leave that for a future patch. Reviewers: spatel Reviewed By: spatel Subscribers: RKSimon, llvm-commits, mehdi_amini Differential Revision: https://reviews.llvm.org/D46498 llvm-svn: 331606
* [X86] Add test cases for reciprocal estimation for v16f32 vectors with AVX512F.Craig Topper2018-05-063-77/+1337
| | | | | | We should be able to use the vrsqrt14ps and vrcp14ps instructions for these cases. llvm-svn: 331605
* Add test cases for large integer legalization of add and sub. NFCAmaury Sechet2018-05-062-0/+62
| | | | llvm-svn: 331604
* [globalisel] Remove redundant -global-isel option from tests that use ↵Daniel Sanders2018-05-05110-178/+178
| | | | | | | | | | | -run-pass. NFC As Roman Tereshin pointed out in https://reviews.llvm.org/D45541, the -global-isel option is redundant when -run-pass is given. -global-isel sets up the GlobalISel passes in the pass manager but -run-pass skips that entirely and configures it's own pipeline. llvm-svn: 331603
* [DAGCombiner] Masked merge: don't touch "not" xor's.Roman Lebedev2018-05-051-11/+9
| | | | | | | | | | | | | | | | | | | | Summary: Split off form D46031. It seems we don't want to transform the pattern if the `xor`'s are actually `not`'s. In vector case, this breaks `andnpd` / `vandnps` patterns. That being said, we may want to re-visit this `not` handling, maybe in D46073. Reviewers: spatel, craig.topper, javed.absar Reviewed By: spatel Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D46492 llvm-svn: 331595
* Mapping SDNode flags to MachineInstr flagsMichael Berg2018-05-041-12/+12
| | | | | | | | | | | | | | Summary: Providing the glue to map SDNode fast math sub flags to MachineInstr fast math sub flags. Reviewers: spatel, arsenm, wristow Reviewed By: spatel Subscribers: wdng Differential Revision: https://reviews.llvm.org/D46447 llvm-svn: 331567
* Fast Math Flag mapping into SDNodeMichael Berg2018-05-041-5/+3
| | | | | | | | | | | | | | Summary: Adding support for Fast flags in the SDNode to leverage fast math sub flag usage. Reviewers: spatel, arsenm, jbhateja, hfinkel, escha, qcolombet, echristo, wristow, javed.absar Reviewed By: spatel Subscribers: llvm-commits, rampitec, nhaehnle, tstellar, FarhanaAleen, nemanjai, javed.absar, jbhateja, hfinkel, wdng Differential Revision: https://reviews.llvm.org/D45710 llvm-svn: 331547
* [X86] Add WriteEMMS scheduler classSimon Pilgrim2018-05-042-6/+6
| | | | | | Filled in the missing values from Btver2 SoG or Agner llvm-svn: 331546
* [X86] Finish splitting WriteVecShift and WriteVecIMul to remove InstRW ↵Simon Pilgrim2018-05-041-3/+3
| | | | | | overrides. llvm-svn: 331543
* [X86] Add test case for PR30290s failing behaviourJeremy Morse2018-05-041-0/+44
| | | | | | | | | Following the advice in review D45022, this currently tests for the broken llc output where an instruction is mis-scheduled. This test is committed in advance to improve the eventual fixing patch in D45022, making the bad behaviour that that patch fixes clearer. llvm-svn: 331514
* Word wrap a test-file comment to 80 columnsJeremy Morse2018-05-041-3/+3
| | | | | | This is a test commit to check whether my account works. llvm-svn: 331512
* [X86][Znver1] Use SchedAlias to tag microcoded scheduler classesSimon Pilgrim2018-05-031-1/+1
| | | | | | | | Avoids extra entries in the class tables. Found a typo that missed the MMX_PHSUBSW instruction. llvm-svn: 331488
* [X86] Split WriteVecShift/WriteVarVecShift into MMX, XMM and YMM/ZMM ↵Simon Pilgrim2018-05-034-64/+64
| | | | | | | | scheduler classes This took a bit of extra work as on Intel targets the old (V)PSLLDrr/(V)PSLLDrm style instructions act differently - I ended up creating WriteVecShiftImm classes for XMM/YMM/ZMM vector shift by immediate and retaining WriteVecShift as the default (used only by MMX) plus WriteVecShiftX/WriteVecShiftY. X86SchedWriteWidths hides most of this thank goodness. llvm-svn: 331472
* [CodeGen][X86][NFC] Copy two selectcc tests from AArch64.Roman Lebedev2018-05-032-0/+227
| | | | | | | | | | | These tests are for DAGCombiner::foldSelectCCToShiftAnd(). Right now, they were only tested for AArch64, but given the upcoming X86 changes to the hasAndNot(), the test coverage needs to be added. These tests originated from D27489 / rL289738 llvm-svn: 331454
* [X86] Split WriteVecALU/WritePHAdd into XMM and YMM/ZMM scheduler classesSimon Pilgrim2018-05-035-224/+224
| | | | llvm-svn: 331453
* [X86] Split WriteVecIMul/WriteVecPMULLD/WriteMPSAD/WritePSADBW into XMM and ↵Simon Pilgrim2018-05-034-40/+40
| | | | | | | | YMM/ZMM scheduler classes Also retagged VDBPSADBW instructions as SchedWritePSADBW instead of SchedWriteVecIMul which matches the behaviour on SkylakeServer (the only thing that supports it...) llvm-svn: 331445
* [X86][SNB] Fix scheduling of MMX integer multiply instructions.Simon Pilgrim2018-05-021-16/+16
| | | | | | The entries were being bound to the wrong class. llvm-svn: 331388
* [X86] Split WriteShuffle/WriteVarShuffle + WriteBlend/WriteVarBlend into XMM ↵Simon Pilgrim2018-05-024-134/+134
| | | | | | and YMM/ZMM scheduler classes llvm-svn: 331386
* [X86] Cleanup WriteFShuffle/WriteFVarShuffle (+256 variants) scheduler ↵Simon Pilgrim2018-05-024-281/+281
| | | | | | classes with more common default values llvm-svn: 331380
* [X86] Cleanup WriteFAdd/WriteFCmp scheduler classes with more common default ↵Simon Pilgrim2018-05-022-23/+23
| | | | | | | | | | values Intel models were targeting x87 instead of packed sse. Also fixes XOP's VFRCZ to use WriteFAdd/WriteFAddY. llvm-svn: 331340
* [DAGCombiner] Fix SDLoc in a (zext (zextload x)) combine (4/N)Vedant Kumar2018-05-011-8/+8
| | | | | | | | | | | | | | | | The logic for this combine is almost identical to the logic for a (sext (sextload x)) combine. This commit factors out the logic so it can be shared by both combines, and corrects the SDLoc assigned in the zext version of the combine. Prior to this patch, for the given test case, we would apply the location associated with the udiv instruction to instructions which perform the load. Part of: llvm.org/PR37262 llvm-svn: 331303
* [DAGCombiner] Change the SDLoc on split extloads (2/N)Vedant Kumar2018-05-017-212/+211
| | | | | | | | | | | | | | | | | | | | | In DAGCombiner, we try to simplify this pattern: ([s|z]ext (load ...)) Conceptually, a new extload which is created while splitting the load should have the same debug location as the load. Making this change affects the IROrder of the new load, causing some test case churn. In practice, the new location is never different from the location of the [s|z]ext, at least not during check-llvm or a stage2 build. Part of: llvm.org/PR37262 Differential Revision: https://reviews.llvm.org/D46156 llvm-svn: 331301
* [DAGCombiner] Set the right SDLoc on a newly-created zextload (1/N)Vedant Kumar2018-05-0111-167/+204
| | | | | | | | | | | | | | | | | | | | | Setting the right SDLoc on a newly-created zextload fixes a line table bug which resulted in non-linear stepping behavior. Several backend tests contained CHECK lines which relied on the IROrder inherited from the wrong SDLoc. This patch breaks that dependence where feasbile and regenerates test cases where not. In some cases, changing a node's IROrder may alter register allocation and spill behavior. This can affect performance. I have chosen not to prevent this by applying a "known good" IROrder to SDLocs, as this may hide a more general bug in the scheduler, or cause regressions on other test inputs. rdar://33755881, Part of: llvm.org/PR37262 Differential Revision: https://reviews.llvm.org/D45995 llvm-svn: 331300
* [X86] Split WriteFMul/WriteFDiv into XMM and YMM/ZMM scheduler classesSimon Pilgrim2018-05-011-7/+7
| | | | llvm-svn: 331293
* [X86] Split WriteFAdd into XMM and YMM/ZMM scheduler classesSimon Pilgrim2018-05-011-12/+12
| | | | | | Removes more WriteFAdd InstRW overrides llvm-svn: 331276
* [DAG] add test to show FMF mismatch between IR and DAG; NFCSanjay Patel2018-05-011-0/+32
| | | | | | | D45710 proposes to change this, but we have no test coverage for the first step in this process. llvm-svn: 331271
* [X86] Split WriteFShuffle into XMM and YMM/ZMM scheduler classesSimon Pilgrim2018-05-011-74/+74
| | | | | | Removes more WriteFShuffle InstRW overrides llvm-svn: 331264
* [X86] Split WriteVecLogic into XMM and YMM/ZMM scheduler classesSimon Pilgrim2018-05-012-5/+5
| | | | | | This removes all the WriteVecLogic InstRW overrides. llvm-svn: 331258
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