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* [X86][AVX2] Add shuffle test for PR27320 showing current codegen.Simon Pilgrim2017-04-251-0/+26
| | | | llvm-svn: 301342
* [X86][AVX2] Add support for combining v16i16 shuffles to VPBLENDWSimon Pilgrim2017-03-281-4/+8
| | | | llvm-svn: 298929
* [X86][SSE] Enable post-legalize vXi64 shuffle combining on 32-bit targetsSimon Pilgrim2017-03-041-1/+1
| | | | | | | | Long ago (2010 according to svn blame), combineShuffle probably needed to prevent the accidental creation of illegal i64 types but there doesn't appear to be any combines that can cause this any more as they all have their own legality checks. Differential Revision: https://reviews.llvm.org/D30213 llvm-svn: 296966
* [X86][AVX] Rename shuffle combine tests to show combined shuffle type. NFCI.Simon Pilgrim2017-02-211-6/+6
| | | | llvm-svn: 295735
* [X86][AVX2] Fix VPBROADCASTQ folding on 32-bit targets.Simon Pilgrim2017-02-211-4/+2
| | | | | | As i64 isn't a value type on 32-bit targets, we need to fold the VZEXT_LOAD into VPBROADCASTQ. llvm-svn: 295733
* [X86][AVX2] Add AVX512 test targets to AVX2 shuffle combines.Simon Pilgrim2017-02-211-24/+50
| | | | llvm-svn: 295731
* [X86][AVX] Add tests showing missed VPBROADCASTQ folding on 32-bit targets.Simon Pilgrim2017-02-211-0/+36
| | | | | | | | As i64 isn't a value type on 32-bit targets, we fail to fold the VZEXT_LOAD into VPBROADCASTQ. Also shows that we're not decoding VPERMIV3 shuffles very well.... llvm-svn: 295729
* [X86][SSE] Allow matchVectorShuffleWithUNPCK to recognise ZERO inputsSimon Pilgrim2017-02-151-4/+8
| | | | | | Add support for specifying an UNPCK input as ZERO, particularly improves ZEXT cases with non-zero offsets llvm-svn: 295169
* [X86][SSE] Allow matchVectorShuffleWithUNPCK to recognise UNDEF inputsSimon Pilgrim2017-02-141-2/+0
| | | | | | Add support for specifying an UNPCK input as UNDEF llvm-svn: 295061
* [X86][SSE] Add shuffle combine tests showing missed opportunities to use UNPCKSimon Pilgrim2017-02-141-0/+43
| | | | | | Not correctly using UNDEF or ZERO inputs to combine to UNPCK shuffles llvm-svn: 295059
* [X86][AVX2] Add support for combining target shuffles to VPMOVZXSimon Pilgrim2017-02-121-4/+2
| | | | | | Initial 256-bit vector support - 512-bit support requires extra checks for AVX512BW support (PMOVZXBW) that will be handled in a future patch. llvm-svn: 294896
* [X86][SSE] Combine shuffle nodes with multiple uses if all the users are ↵Simon Pilgrim2017-02-061-12/+2
| | | | | | | | | | | | | | being combined. Currently we only combine shuffle nodes if they have a single user to prevent us from causing code bloat by splitting the shuffles into several different combines. We don't take into account that in some cases we will already have combined all the users during recursively calling up the shuffle tree. This patch keeps a list of all the shuffle nodes that have been combined so far and permits combining of further shuffle nodes if all its users are in that list. Differential Revision: https://reviews.llvm.org/D29399 llvm-svn: 294183
* [X86][SSE] Add target shuffle combine buildvec style testsSimon Pilgrim2017-02-041-0/+29
| | | | | | Extra tests for D29399 llvm-svn: 294101
* [X86][SSE] Add support for combining AND bitmasks to shuffles.Simon Pilgrim2016-12-011-4/+2
| | | | llvm-svn: 288365
* [X86][SSE] Add support for combining target shuffles to AND bitmasks.Simon Pilgrim2016-12-011-6/+6
| | | | llvm-svn: 288335
* [X86][SSE] Add support for combining ISD::AND with shuffles.Simon Pilgrim2016-12-011-2/+0
| | | | | | Attempts to convert an AND with a vector of 255 or 0 values into a shuffle (blend) mask. llvm-svn: 288333
* [X86][SSE] Added tests showing missed combines of shuffles with ANDs.Simon Pilgrim2016-12-011-0/+17
| | | | llvm-svn: 288330
* [X86][SSE] Added tests showing missed combines of ANDs with shuffles.Simon Pilgrim2016-11-301-0/+17
| | | | llvm-svn: 288259
* [X86][SSE] Add support for target shuffle constant foldingSimon Pilgrim2016-11-301-12/+6
| | | | | | | | | | Initial support for target shuffle constant folding in cases where all shuffle inputs are constant. We may be able to relax this and merge shuffles with only some constant inputs in the future. I've added the helper function getTargetConstantBitsFromNode (based off a similar function in X86ShuffleDecodeConstantPool.cpp) that could be reused for other cases requiring constant vector extraction. Differential Revision: https://reviews.llvm.org/D27220 llvm-svn: 288250
* [X86][SSE] Added tests showing missed combines to (V)PMOVZXSimon Pilgrim2016-11-291-0/+38
| | | | llvm-svn: 288136
* [X86][SSE] Added support for combining bit-shifts with shuffles.Simon Pilgrim2016-11-281-12/+6
| | | | | | | | Bit-shifts by a whole number of bytes can be represented as a shuffle mask suitable for combining. Added a 'getFauxShuffleMask' function to allow us to create shuffle masks from other suitable operations. llvm-svn: 288040
* [X86][SSE] Added tests showing missed combines of shifts with shuffles.Simon Pilgrim2016-11-281-0/+54
| | | | llvm-svn: 288037
* [X86][SSE] Add support for combining target shuffles to 128/256-bit ↵Simon Pilgrim2016-11-271-6/+6
| | | | | | PSLL/PSRL bit shifts llvm-svn: 288006
* [X86][SSE] Added tests showing missed combines for shuffle to shifts.Simon Pilgrim2016-11-271-0/+42
| | | | llvm-svn: 288000
* [X86][AVX2] Add support for combining target shuffles to VPERMD/VPERMPSSimon Pilgrim2016-10-021-21/+9
| | | | llvm-svn: 283080
* [X86][AVX2] Missed opportunities to combine to VPERMD/VPERMPSSimon Pilgrim2016-10-021-0/+48
| | | | llvm-svn: 283077
* [X86][AVX2] Fix typo in test namesSimon Pilgrim2016-10-021-6/+6
| | | | | | We are testing vpermps not vpermd llvm-svn: 283076
* [X86][AVX] Test target shuffle combining on 32 and 64-bit targetsSimon Pilgrim2016-09-171-155/+344
| | | | llvm-svn: 281833
* [X86][AVX2] Add target shuffle constant folding testsSimon Pilgrim2016-09-171-0/+30
| | | | llvm-svn: 281830
* [X86][SSE] Generalised combining to VZEXT_MOVL to any vector sizeSimon Pilgrim2016-08-191-0/+24
| | | | | | This doesn't change tests codegen as we already combined to blend+zero which is what we lower VZEXT_MOVL to on SSE41+ targets, but it does put us in a better position when we improve shuffling for optsize. llvm-svn: 279273
* [X86][SSE] Add support for combining target shuffles to PSLLDQ/PSRLDQ byte ↵Simon Pilgrim2016-08-121-2/+2
| | | | | | shifts llvm-svn: 278502
* [X86][AVX] Add target shuffle decode support for VBROADCASTSimon Pilgrim2016-07-181-4/+0
| | | | | | Currently we only decode broadcasts from a vector of the same size. llvm-svn: 275823
* [X86][AVX2] Added tests that demonstrate duplicate broadcastsSimon Pilgrim2016-07-181-0/+60
| | | | | | We don't yet decode broadcasts as a target shuffle llvm-svn: 275808
* [X86][AVX] Add support for narrowing 128-bit+ shuffle mask elements to ↵Simon Pilgrim2016-07-141-2/+2
| | | | | | | | 64-bits to allow combining Primarily this is to allow blend with zero instead of having to use vperm2f128, but we can use this in the future to deal with AVX512 cases where we need to keep the original element size to correctly fold masked operations. llvm-svn: 275406
* [X86][AVX] Add 128-bit wide shuffle tests that should combine to blend-with-zeroSimon Pilgrim2016-07-141-0/+12
| | | | llvm-svn: 275402
* [X86][AVX] Add support for target shuffle combining to VPERM2F128/VPERM2I128Simon Pilgrim2016-07-121-6/+7
| | | | llvm-svn: 275212
* [X86][SSE] Add support for target shuffle combining to PSHUFLW/PSHUFHWSimon Pilgrim2016-07-101-4/+4
| | | | llvm-svn: 275022
* [X86][SSE] Added tests for combining shuffles to PSHUFLW/PSHUFHWSimon Pilgrim2016-07-101-0/+28
| | | | llvm-svn: 275019
* VirtRegMap: Replace some identity copies with KILL instructions.Matthias Braun2016-07-091-0/+6
| | | | | | | | | | | | | | An identity COPY like this: %AL = COPY %AL, %EAX<imp-def> has no semantic effect, but encodes liveness information: Further users of %EAX only depend on this instruction even though it does not define the full register. Replace the COPY with a KILL instruction in those cases to maintain this liveness information. (This reverts a small part of r238588 but this time adds a comment explaining why a KILL instruction is useful). llvm-svn: 274952
* [X86][AVX2] Add support for target shuffle combining to VPERMPD/VPERMQSimon Pilgrim2016-07-081-0/+18
| | | | llvm-svn: 274908
* [X86][SSE] Added test cases for missed opportunities to combine pshufb to ↵Simon Pilgrim2016-07-061-0/+18
| | | | | | pslldq/psrldq llvm-svn: 274631
* [X86][AVX2] Add support for target shuffle combining to BROADCASTSimon Pilgrim2016-07-051-0/+124
| | | | | | Only support broadcast from vector register so far - memory folding support will have to wait. llvm-svn: 274572
* [X86][SSE] Added support for combining target shuffles to ↵Simon Pilgrim2016-06-281-1/+1
| | | | | | | | | | | | (V)PSHUFD/VPERMILPD/VPERMILPS immediate permutes This patch allows target shuffles to be combined to single input immediate permute instructions - (V)PSHUFD/VPERMILPD/VPERMILPS - allowing more general pattern matching than what we current do and improves the likelihood of memory folding compared to existing patterns which tend to reuse the input in multiple arguments. Further permute instructions (V)PSHUFLW/(V)PSHUFHW/(V)PERMQ/(V)PERMPD may be added in the future but its proven tricky to create tests cases for them so far. (V)PSHUFLW/(V)PSHUFHW is already handled quite well in combineTargetShuffle so it may be that removing some of that code may allow us to perform more of the combining in one place without duplication. Differential Revision: http://reviews.llvm.org/D21148 llvm-svn: 273999
* [X86][SSE] Added PSLLDQ/PSRLDQ as a target shuffle typeSimon Pilgrim2016-06-111-4/+2
| | | | | | Ensure that PALIGNR/PSLLDQ/PSRLDQ are byte vectors so that they can be correctly decoded for target shuffle combining llvm-svn: 272471
* [X86][AVX2] Added PSLLDQ/PSRLDQ shuffle combining testsSimon Pilgrim2016-06-111-0/+22
| | | | llvm-svn: 272469
* [X86][AVX2] Added 128-bit wide shuffle testSimon Pilgrim2016-05-021-0/+14
| | | | | | Demonstrate missing 128-bit wide shuffle combine support llvm-svn: 268290
* [X86] Don't assume that shuffle non-mask operands starts at #0.Ahmed Bougacha2016-03-031-0/+27
That's not the case for VPERMV/VPERMV3, which cover all possible combinations (the C intrinsics use a different order; the AVX vs AVX512 intrinsics are different still). Since: r246981 AVX-512: Lowering for 512-bit vector shuffles. VPERMV is recognized in getTargetShuffleMask. This breaks assumptions in most callers, as they expect the non-mask operands to start at index 0. VPERMV has the mask as operand #0; VPERMV3 has it in the middle. Instead of the faulty assumption, have getTargetShuffleMask return its operands as well. One alternative we considered was to change the operand order of VPERMV, but we agreed to stick to the instruction order, as there are more AVX512 weirdness to cover (vpermt2/vpermi2 in particular). Differential Revision: http://reviews.llvm.org/D17041 llvm-svn: 262627
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