summaryrefslogtreecommitdiffstats
path: root/llvm/test/CodeGen/X86/vector-rotate-256.ll
Commit message (Collapse)AuthorAgeFilesLines
* [DAG] add splat vector support for 'and' in SimplifyDemandedBitsSanjay Patel2017-04-191-14/+3
| | | | | | | | | | | | | | | | | | | | | The patch itself is simple: stop discriminating against vectors in visitAnd() and again in SimplifyDemandedBits(). Some notes for reference: 1. We're not consistent about calls to SimplifyDemandedBits in the various visitXXX functions. Sometimes, we check if the RHS is a constant first. Other times (like here), we just dive in. 2. I'd like to break the vector shackles in steps for the sake of risk minimization, but we could make similar simultaneous changes in other places if we think that would be better. 3. I don't know what the intent of the changed tests in this patch was supposed to be, but since they wiggled in a positive way, I'm just going with that. :) 4. In the rotate tests, note that we can see through non-splat constants. This is a result of D24253. 5. My motivation for being here now is to make D31944 look better, so this is step 1 of N towards improving the vector codegen in that patch without writing any actual new code. Differential Revision: https://reviews.llvm.org/D32230 llvm-svn: 300725
* [X86][AVX512] Add vector rotate tests for AVX512 targetsSimon Pilgrim2017-02-101-0/+177
| | | | | | AVX512 does have vector rotate instructions, but we don't lower to them yet llvm-svn: 294766
* [X86][SSE] Add support for constant folding vector logical shift by immediatesSimon Pilgrim2017-01-241-26/+22
| | | | llvm-svn: 292915
* [X86][AVX2] Fix v16i16 SHL lowering (PR27730)Simon Pilgrim2016-06-041-6/+6
| | | | | | | | The AVX2 v16i16 shift lowering works by unpacking to 2 x v8i32, performing the shift and then truncating the result. The unpacking is used to place the values in the upper 16-bits so that we can correctly sign-extend for SRA shifts. Unfortunately we weren't ensuring that the lower 16-bits were zero to ensure that SHL correctly shifts in zero bits. llvm-svn: 271796
* [X86][SSE41] Avoid variable blend for constant v8i16 shiftsSimon Pilgrim2016-03-131-16/+8
| | | | | | The SSE41 v8i16 shift lowering using (v)pblendvb is great for non-constant shift amounts, but if it is constant then we can efficiently reduce the VSELECT to shuffles with the pre-SSE41 lowering. llvm-svn: 263383
* [X86][SSE] Fixed vector rotation test name typoSimon Pilgrim2016-02-241-5/+5
| | | | | | Rotation of 16i6 vector not 8i16 vector - copy+paste is not your friend llvm-svn: 261733
* Make utils/update_llc_test_checks.py note that the assertions areJames Y Knight2015-11-231-0/+1
| | | | | | | | | autogenerated. Also update existing test cases which appear to be generated by it and weren't modified (other than addition of the header) by rerunning it. llvm-svn: 253917
* [X86][SSE] shift/rotate tests - remove unnecessary mcpu arguments and ↵Simon Pilgrim2015-10-251-4/+4
| | | | | | regenerate/cleanup llvm-svn: 251232
* [DAGCombiner] Generalize masking of constant rotates.Simon Pilgrim2015-10-241-23/+15
| | | | | | | | We don't need a mask of a rotation result to be a constant splat - any constant scalar/vector can be usefully folded. Followup to D13851. llvm-svn: 251197
* [X86][XOP] Add support for lowering vector rotationsSimon Pilgrim2015-10-241-209/+105
| | | | | | | | | | This patch adds support for lowering to the XOP VPROT / VPROTI vector bit rotation instructions. This has required changes to the DAGCombiner rotation pattern matching to support vector types - so far I've only changed it to support splat vectors, but generalising this further is feasible in the future. Differential Revision: http://reviews.llvm.org/D13851 llvm-svn: 251188
* [X86][SSE] Add 256-bit vector bit rotation tests.Simon Pilgrim2015-10-201-0/+1200
llvm-svn: 250853
OpenPOWER on IntegriCloud