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* Followup on Proposal to move MIR physical register namespace to '$' sigil.Puyan Lotfi2018-01-311-10/+10
| | | | | | | | | | | | Discussed here: http://lists.llvm.org/pipermail/llvm-dev/2018-January/120320.html In preparation for adding support for named vregs we are changing the sigil for physical registers in MIR to '$' from '%'. This will prevent name clashes of named physical register with named vregs. llvm-svn: 323922
* DAGCombine: Let truncates negate extension through extract-subvectorZvi Rackover2018-01-111-66/+21
| | | | | | | | | | | | | | | | | | | | | | Summary: Fold cases such as: (v8i8 truncate (v8i32 extract_subvector (v16i32 sext (v16i8 V), Idx))) -> (v8i8 extract_subvector (v16i8 V), Idx) This can be generalized to cases where the truncate and extend do not fully cancel each other out, but it may require querying the target about profitability. Reviewers: RKSimon, craig.topper, spatel, efriedma Reviewed By: RKSimon Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D41927 llvm-svn: 322300
* X86 Tests: Add zext cases in (trunc (subvector)) test. NFCZvi Rackover2018-01-111-0/+138
| | | | | | Cases were missing as observed in D41927 llvm-svn: 322297
* X86 Tests: Add isel tests for truncate-extract_vector-extend. NFC.Zvi Rackover2018-01-101-0/+160
To be improved in a future patch llvm-svn: 322192
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