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* Enable MI Sched for x86.Andrew Trick2013-10-151-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | This changes the SelectionDAG scheduling preference to source order. Soon, the SelectionDAG scheduler can be bypassed saving a nice chunk of compile time. Performance differences that result from this change are often a consequence of register coalescing. The register coalescer is far from perfect. Bugs can be filed for deficiencies. On x86 SandyBridge/Haswell, the source order schedule is often preserved, particularly for small blocks. Register pressure is generally improved over the SD scheduler's ILP mode. However, we are still able to handle large blocks that require latency hiding, unlike the SD scheduler's BURR mode. MI scheduler also attempts to discover the critical path in single-block loops and adjust heuristics accordingly. The MI scheduler relies on the new machine model. This is currently unimplemented for AVX, so we may not be generating the best code yet. Unit tests are updated so they don't depend on SD scheduling heuristics. llvm-svn: 192750
* Revert "Temporarily enable MI-Sched on X86."Andrew Trick2013-06-251-1/+1
| | | | | | This reverts commit 98a9b72e8c56dc13a2617de84503a3d78352789c. llvm-svn: 184823
* Temporarily enable MI-Sched on X86.Andrew Trick2013-06-241-1/+1
| | | | | | | Sorry for the unit test churn. I'll try to make the change permanently next time. llvm-svn: 184705
* Ensure CopyToReg nodes are always glued to the call instruction.Jakob Stoklund Olesen2012-07-041-5/+5
| | | | | | | | | | | | | The CopyToReg nodes that set up the argument registers before a call must be glued to the call instruction. Otherwise, the scheduler may emit the physreg copies long before the call, causing long live ranges for the fixed registers. Besides disabling good register allocation, that can also expose problems when EmitInstrWithCustomInserter() splits a basic block during the live range of a physreg. llvm-svn: 159721
* Use pushq / popq instead of subq $8, %rsp / addq $8, %rsp to adjust stack inEvan Cheng2011-01-031-4/+4
| | | | | | | | | | | prologue and epilogue if the adjustment is 8. Similarly, use pushl / popl if the adjustment is 4 in 32-bit mode. In the epilogue, takes care to pop to a caller-saved register that's not live at the exit (either return or tailcall instruction). rdar://8771137 llvm-svn: 122783
* Do not force indirect tailcall through fixed registers: eax, r11. Add ↵Evan Cheng2010-03-141-4/+4
| | | | | | support to allow loads to be folded to tail call instructions. llvm-svn: 98465
* Fix http://llvm.org/PR5729: x86-64 tail calls were putting their targets intoJeffrey Yasskin2010-01-091-0/+71
R11, and then asserting that the target was in R9. Since R9 isn't reserved for the target anymore, and is used as an argument, this patch changes the assertion. llvm-svn: 93065
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