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* [X86] No need to avoid selecting AVX_SET0 for 256-bit integer types when ↵Craig Topper2016-05-081-2/+2
| | | | | | only AVX1 is supported. AVX_SET0 just expands to 256-bit VXORPS which is legal in AVX1. llvm-svn: 268871
* [X86][SSE] Added tests to ensure that consecutive loads including any/all ↵Simon Pilgrim2016-03-241-0/+113
| | | | | | volatiles are not combined llvm-svn: 264225
* [X86][SSE] Simplified blend-with-zero combiningSimon Pilgrim2016-03-171-2/+2
| | | | | | | | We were being too aggressive in trying to combine a shuffle into a blend-with-zero pattern, often resulting in a endless loop of contrasting combines This patch stops the combine if we already have a blend in place (means we miss some domain corrections) llvm-svn: 263717
* [X86][SSE41] Combine vector blends with zeroSimon Pilgrim2016-02-241-2/+2
| | | | | | | | | Part 2 of 2 This patch add support for combining target shuffles into blends-with-zero. Differential Revision: http://reviews.llvm.org/D17483 llvm-svn: 261745
* [X86][AVX] Add shuffle masking support for EltsFromConsecutiveLoadsSimon Pilgrim2016-02-211-119/+32
| | | | | | | | Add support for the case where we have a consecutive load (which must include the first + last elements) with a mixture of undef/zero elements. We load the vector and then apply a shuffle to clear the zero'd elements. Differential Revision: http://reviews.llvm.org/D17297 llvm-svn: 261490
* [X86][SSE] Added support for MOVHPD/MOVLPD + MOVHPS/MOVLPS shuffle decoding.Simon Pilgrim2016-02-071-3/+3
| | | | llvm-svn: 260034
* [X86][SSE] Select domain for 32/64-bit partial loads for ↵Simon Pilgrim2016-02-041-7/+7
| | | | | | | | | | EltsFromConsecutiveLoads Choose between MOVD/MOVSS and MOVQ/MOVSD depending on the target vector type. This has a lot fewer test changes than trying to add this to X86InstrInfo::setExecutionDomain..... llvm-svn: 259816
* [X86][SSE] Add general 32-bit LOAD + VZEXT_MOVL support to ↵Simon Pilgrim2016-02-041-64/+12
| | | | | | | | | | EltsFromConsecutiveLoads This patch adds support for consecutive (load/undef elements) 32-bit loads, followed by trailing undef/zero elements to be combined to a single MOVD load. Differential Revision: http://reviews.llvm.org/D16729 llvm-svn: 259796
* [X86][SSE] Added i686 target tests to make sure we are correctly loading ↵Simon Pilgrim2016-02-041-0/+191
| | | | | | consecutive entries as 64-bit integers llvm-svn: 259794
* [X86][AVX] Add support for 64-bit VZEXT_LOAD of 256/512-bit vectors to ↵Simon Pilgrim2016-02-031-20/+4
| | | | | | | | | | | | EltsFromConsecutiveLoads Follow up to D16217 and D16729 This change uncovered an odd pattern where VZEXT_LOAD v4i64 was being lowered to a load of the lower v2i64 (so the 2nd i64 destination element wasn't being zeroed), I can't find any use/reason for this and have removed the pattern and replaced it so only the 1st i64 element is loaded and the upper bits all zeroed. This matches the description for X86ISD::VZEXT_LOAD Differential Revision: http://reviews.llvm.org/D16768 llvm-svn: 259635
* [X86][AVX512] Add support for AVX512 VMOVQ (load) shuffle decodingSimon Pilgrim2016-02-021-14/+4
| | | | llvm-svn: 259496
* [X86][AVX512] Add support for AVX512 VMOVD (load) shuffle decodingSimon Pilgrim2016-02-011-4/+4
| | | | llvm-svn: 259430
* [X86][AVX512] Add support for AVX512 VMOVSD/VMOVSS shuffle decodingSimon Pilgrim2016-02-011-18/+8
| | | | llvm-svn: 259427
* [X86][AVX512] Add support for AVX512 VINSERTPS shuffle decodingSimon Pilgrim2016-02-011-1/+1
| | | | llvm-svn: 259420
* [X86][SSE] Add AVX512 merge consecutive load testsSimon Pilgrim2016-02-011-33/+150
| | | | | | | | Add AVX512F/AVX512BW 512-bit tests. Add AVX512F tests to existing 128/256-bit tests. llvm-svn: 259410
* [X86][AVX] Added more thorough 256-bit vector consecutive load tests.Simon Pilgrim2016-01-281-0/+419
| | | | llvm-svn: 259100
* [X86][SSE] Added more exhaustive merge consecutive load testsSimon Pilgrim2016-01-151-0/+91
llvm-svn: 257876
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