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path: root/llvm/test/CodeGen/X86/known-signbits-vector.ll
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* [CodeGen] Unify MBB reference format in both MIR and debug outputFrancis Visoiu Mistrih2017-12-041-22/+22
| | | | | | | | | | | | | | | | As part of the unification of the debug format and the MIR format, print MBB references as '%bb.5'. The MIR printer prints the IR name of a MBB only for block definitions. * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)->getNumber\(\)/" << printMBBReference(*\1)/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)\.getNumber\(\)/" << printMBBReference(\1)/g' * find . \( -name "*.txt" -o -name "*.s" -o -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#([0-9]+)/%bb.\1/g' * grep -nr 'BB#' and fix Differential Revision: https://reviews.llvm.org/D40422 llvm-svn: 319665
* [SelectionDAG] Add SELECT demanded elts support to ComputeNumSignBitsSimon Pilgrim2017-10-301-36/+7
| | | | llvm-svn: 316933
* [X86][SSE] ComputeNumSignBits tests showing missing VSELECT demandedelts ↵Simon Pilgrim2017-10-301-0/+107
| | | | | | support llvm-svn: 316932
* [SelectionDAG] Add SEXT/AND/XOR/Or demanded elts support to ComputeNumSignBitsSimon Pilgrim2017-10-291-23/+15
| | | | llvm-svn: 316875
* [X86][SSE] Split ComputeNumSignBits SEXT/AND/XOR/OR demandedelts testSimon Pilgrim2017-10-291-17/+65
| | | | | | Max depth was being exceeded which could prevent some combines working llvm-svn: 316871
* [X86][SSE] ComputeNumSignBits tests showing missing SEXT/AND/XOR/OR ↵Simon Pilgrim2017-10-291-0/+68
| | | | | | demandedelts support llvm-svn: 316868
* [SelectionDAG] Add SRA/SHL demanded elts support to ComputeNumSignBitsSimon Pilgrim2017-10-291-24/+14
| | | | | | Introduce a isConstOrDemandedConstSplat helper function that can recognise a constant splat build vector for at least the demanded elts we care about. llvm-svn: 316866
* [X86][SSE] ComputeNumSignBits tests showing missing SHL/SRA demandedelts ↵Simon Pilgrim2017-10-291-3/+90
| | | | | | support llvm-svn: 316865
* [X86][SSE] Add extractps/pextrd equivalence to domain tablesSimon Pilgrim2017-10-211-1/+1
| | | | | | Differential Revision: https://reviews.llvm.org/D39135 llvm-svn: 316274
* [X86][AVX] Allow 32-bit targets to peek through subvectors to extract ↵Simon Pilgrim2017-05-141-8/+1
| | | | | | constant splats for vXi64 shifts. llvm-svn: 303009
* [SelectionDAG] Added support for EXTRACT_SUBVECTOR/CONCAT_VECTORS ↵Simon Pilgrim2017-05-131-23/+4
| | | | | | demandedelts in ComputeNumSignBits llvm-svn: 302997
* [X86][SSE] Test showing missing EXTRACT_SUBVECTOR/CONCAT_VECTORS ↵Simon Pilgrim2017-05-131-0/+55
| | | | | | demandedelts support in ComputeNumSignBits llvm-svn: 302994
* [SelectionDAG] Add VECTOR_SHUFFLE support to ComputeNumSignBitsSimon Pilgrim2017-05-131-45/+5
| | | | llvm-svn: 302993
* [X86][SSE] Test showing inability of ComputeNumSignBits to resolve shufflesSimon Pilgrim2017-05-131-0/+72
| | | | llvm-svn: 302992
* [DAGCombiner] Add ComputeNumSignBits vector demanded elements support to ↵Simon Pilgrim2017-04-281-17/+11
| | | | | | | | ASHR and INSERT_VECTOR_ELT (reapplied) Reapplied r299221 after fix for nondeterminism in ThinLTO builder (rL301599), with extra check for implicit truncation of inserted element. llvm-svn: 301644
* Temporarily revert r299221 to fix nondeterminism in ThinLTO builder.Galina Kistanova2017-04-191-11/+17
| | | | llvm-svn: 300783
* [DAGCombiner] Add ComputeNumSignBits vector demanded elements support to ↵Simon Pilgrim2017-03-311-17/+11
| | | | | | | | ASHR and INSERT_VECTOR_ELT Followup to D31311 llvm-svn: 299221
* [X86][SSE] Add extra computeNumSignBits test case for D31311.Simon Pilgrim2017-03-251-0/+47
| | | | llvm-svn: 298774
* [X86][SSE] Extract elements from narrower shuffle masks.Simon Pilgrim2017-03-231-5/+2
| | | | | | Add support for widening narrow shuffle masks so we can directly extract from the relevant input vector of the shuffle. llvm-svn: 298616
* [X86][SSE] Add computeNumSignBits test for sitofp of (extended) i64 ↵Simon Pilgrim2017-03-231-0/+28
| | | | | | extracted element llvm-svn: 298592
* [X86][SSE] Fix load folding for (V)CVTDQ2PDSimon Pilgrim2017-03-101-2/+1
| | | | | | This only requires a 64-bit memory source, not the whole 128-bits. But the 128-bit case is still supported via X86InstrInfo::foldMemoryOperandImpl llvm-svn: 297523
* [SelectionDAG] Add support for BUILD_VECTOR to ComputeNumSignBitsSimon Pilgrim2017-03-101-63/+28
| | | | llvm-svn: 297492
* [X86][SSE] Added tests showing missed truncations for sitofp conversionSimon Pilgrim2017-03-101-0/+109
SelectionDAG::ComputeNumSignBits is poor at build_vector handling, meaning that we can't see that all the vXi64 sources are in fact sign extended i32 or smaller. llvm-svn: 297486
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