| Commit message (Collapse) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | Split the Add, Sub, and Mul instruction opcodes into separate | Dan Gohman | 2009-06-04 | 1 | -1/+1 |
| | | | | | | | | | | | | | | | | integer and floating-point opcodes, introducing FAdd, FSub, and FMul. For now, the AsmParser, BitcodeReader, and IRBuilder all preserve backwards compatability, and the Core LLVM APIs preserve backwards compatibility for IR producers. Most front-ends won't need to change immediately. This implements the first step of the plan outlined here: http://nondot.org/sabre/LLVMNotes/IntegerOverflow.txt llvm-svn: 72897 | ||||
| * | Implement basic support for the 'f' register class constraint. This basically | Chris Lattner | 2008-03-11 | 1 | -0/+14 |
| | | | | | | | works, but probably won't if you mix it with 't' or 'u' yet. llvm-svn: 48243 | ||||
| * | teach X86InstrInfo::copyRegToReg how to copy into ST(0) from | Chris Lattner | 2008-03-09 | 1 | -0/+16 |
| | | | | | | | | | | | | | an RFP register class. Teach ScheduleDAG how to handle CopyToReg with different src/dst reg classes. This allows us to compile trivial inline asms that expect stuff on the top of x87-fp stack. llvm-svn: 48107 | ||||
| * | Add ScheduleDAG support for copytoreg where the src/dst register are | Chris Lattner | 2008-03-09 | 1 | -0/+13 |
| in different register classes, e.g. copy of ST(0) to RFP*. This gets some really trivial inline asm working that plops things on the top of stack (PR879) llvm-svn: 48105 | |||||
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index : bcm5719-llvm | |
| Project Ortega BCM5719 LLVM | Raptor Computing Systems |
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