bcm5719-llvm - Project Ortega BCM5719 LLVM

	Commit message (Expand)	Author	Age	Files	Lines
*	[x86] split more v8f32/v8i32 shuffles in lowering	Sanjay Patel	2019-02-18	1	-5/+5
*	[SelectionDAG] Optional handling of UNDEF elements in matchUnaryPredicate	Simon Pilgrim	2018-12-19	1	-8/+3
*	[X86][SSE] Add shift combine 'out of range' tests with UNDEFs	Simon Pilgrim	2018-12-18	1	-0/+13
*	[X86][SSE] Add computeKnownBits/ComputeNumSignBits support for PACKSS/PACKUS ...	Simon Pilgrim	2018-11-20	1	-19/+1
*	[X86][SSE] Remove unnecessary bit-and in pshufb vector ctlz (PR39703)	Simon Pilgrim	2018-11-19	1	-34/+32
*	[X86] Add vector shift by immediate to SimplifyDemandedBitsForTargetNode.	Craig Topper	2018-11-04	1	-11/+1
*	[X86] Move promotion of vector and/or/xor from legalization to DAG combine	Craig Topper	2018-10-15	1	-35/+30
*	[X86][SSE] Reduce instruction/register usages for v4i32 vector shifts (PR37441)	Simon Pilgrim	2018-05-16	1	-15/+13
*	[x86] remove duplicate undef tests; NFC	Sanjay Patel	2018-02-09	1	-18/+0
*	[X86] Add common CHECK prefix to shift combine tests	Simon Pilgrim	2018-02-08	1	-40/+19
*	[X86] Add shift undef, %X tests	Simon Pilgrim	2018-02-08	1	-0/+27
*	X86 Tests: Update more isel tests with FastVariableShuffle feature	Zvi Rackover	2018-01-09	1	-17/+36
*	[CodeGen] Unify MBB reference format in both MIR and debug output	Francis Visoiu Mistrih	2017-12-04	1	-40/+40
*	[SelectionDAG] Teach computeKnownBits some improvements to ISD::SRL with a no...	Craig Topper	2017-12-04	1	-6/+6
*	[X86][SSE] Add PACKUS support to combineVectorTruncation	Simon Pilgrim	2017-11-03	1	-1/+1
*	[X86][SSE] Add PACKUS support to LowerTruncate	Simon Pilgrim	2017-11-01	1	-3/+2
*	[DAGCombiner] Match ISD::SRL non-uniform constant vectors patterns using pred...	Simon Pilgrim	2017-07-20	1	-42/+10
*	[X86][AVX] Regenerate combine tests with constant broadcast comments	Simon Pilgrim	2017-07-16	1	-4/+4
*	[DAGCombiner] Add vector support to fold (shl/srl 0, x) -> 0	Simon Pilgrim	2017-05-10	1	-20/+2
*	[DAGCombiner] Add vector support for (srl (trunc (srl x, c1)), c2) combine.	Simon Pilgrim	2017-04-25	1	-5/+4
*	[x86] use a single shufps when it can save instructions	Sanjay Patel	2016-12-15	1	-30/+22
*	[DAG] enhance computeKnownBits to handle SRL/SRA with vector splat constant	Sanjay Patel	2016-10-23	1	-16/+4
*	[DAGCombiner] Add general constant vector support to (srl (shl x, c), c) -> (...	Simon Pilgrim	2016-10-20	1	-14/+2
*	[DAGCombine] Generalize distributeTruncateThroughAnd to work with any non-opa...	Simon Pilgrim	2016-10-19	1	-3/+2
*	[X86][SSE] Added vector lshr/shl combine tests	Simon Pilgrim	2016-10-18	1	-0/+546