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* Recommit r368079 "[X86] Remove uses of the ↵Craig Topper2019-08-071-72/+0
| | | | | | -x86-experimental-vector-widening-legalization flag from test/CodeGen/X86/" llvm-svn: 368184
* Recommit r367901 "[X86] Enable ↵Craig Topper2019-08-071-7/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | -x86-experimental-vector-widening-legalization by default." The assert that caused this to be reverted should be fixed now. Original commit message: This patch changes our defualt legalization behavior for 16, 32, and 64 bit vectors with i8/i16/i32/i64 scalar types from promotion to widening. For example, v8i8 will now be widened to v16i8 instead of promoted to v8i16. This keeps the elements widths the same and pads with undef elements. We believe this is a better legalization strategy. But it carries some issues due to the fragmented vector ISA. For example, i8 shifts and multiplies get widened and then later have to be promoted/split into vXi16 vectors. This has the potential to cause regressions so we wanted to get it in early in the 10.0 cycle so we have plenty of time to address them. Next steps will be to merge tests that explicitly test the command line option. And then we can remove the option and its associated code. llvm-svn: 368183
* Revert "[X86] Enable -x86-experimental-vector-widening-legalization by default."Mitch Phillips2019-08-061-6/+7
| | | | | | | | | This reverts commit 3de33245d2c992c9e0af60372043540b60f3a810. This commit broke the MSan buildbots. See https://reviews.llvm.org/rL367901 for more information. llvm-svn: 368107
* Revert "[X86] Remove uses of the ↵Mitch Phillips2019-08-061-0/+72
| | | | | | | | | | | | | | -x86-experimental-vector-widening-legalization flag from test/CodeGen/X86/" This reverts commit 3f572c7b8405f36993ec8a226dcddd57283a7c1e. The MSan sanitizer buildbot was broken by rL367901. This commit (rL368079) depends on the broken commit that need to be reverted, and thus itself is being reverted. See https://reviews.llvm.org/rL367901 for more information. llvm-svn: 368106
* [X86] Remove uses of the -x86-experimental-vector-widening-legalization flag ↵Craig Topper2019-08-061-72/+0
| | | | | | | | | | | | from test/CodeGen/X86/ This flag is now the default behavior so we no longer need to set it in tests. Some redundant tests have been removed after verifying we have an equivalent test that didn't use the flag. llvm-svn: 368079
* [X86] Enable -x86-experimental-vector-widening-legalization by default.Craig Topper2019-08-051-7/+6
| | | | | | | | | | | | | | | | | | | | | This patch changes our defualt legalization behavior for 16, 32, and 64 bit vectors with i8/i16/i32/i64 scalar types from promotion to widening. For example, v8i8 will now be widened to v16i8 instead of promoted to v8i16. This keeps the elements widths the same and pads with undef elements. We believe this is a better legalization strategy. But it carries some issues due to the fragmented vector ISA. For example, i8 shifts and multiplies get widened and then later have to be promoted/split into vXi16 vectors. This has the potential to cause regressions so we wanted to get it in early in the 10.0 cycle so we have plenty of time to address them. Next steps will be to merge tests that explicitly test the command line option. And then we can remove the option and its associated code. llvm-svn: 367901
* [DAGCombiner] don't group bswap with casts in logic hoisting foldSanjay Patel2018-12-061-25/+11
| | | | | | | | | | | | | | | | This was probably organized as it was because bswap is a unary op. But that's where the similarity to the other opcodes ends. We should not limit this transform to scalars, and we should not try it if either input has other uses. This is another step towards trying to clean this whole function up to prevent it from causing infinite loops and memory explosions. Earlier commits in this series: rL348501 rL348508 rL348518 llvm-svn: 348534
* [x86] add test for vector bitwise-logic-of-bswaps; NFCSanjay Patel2018-12-061-5/+56
| | | | llvm-svn: 348530
* [CodeGen] Unify MBB reference format in both MIR and debug outputFrancis Visoiu Mistrih2017-12-041-53/+53
| | | | | | | | | | | | | | | | As part of the unification of the debug format and the MIR format, print MBB references as '%bb.5'. The MIR printer prints the IR name of a MBB only for block definitions. * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)->getNumber\(\)/" << printMBBReference(*\1)/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)\.getNumber\(\)/" << printMBBReference(\1)/g' * find . \( -name "*.txt" -o -name "*.s" -o -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#([0-9]+)/%bb.\1/g' * grep -nr 'BB#' and fix Differential Revision: https://reviews.llvm.org/D40422 llvm-svn: 319665
* [X86][SSE] Dropped -mcpu from vector bswap testsSimon Pilgrim2017-06-281-7/+4
| | | | | | Use triple and attribute only for consistency llvm-svn: 306545
* [X86][SSE] Add support for combining SSE VSHLI/VSRLI uniform constant shifts.Simon Pilgrim2016-12-121-4/+2
| | | | | | Fixes some missed constant folding opportunities and allows us to combine shuffles that end with a logical bit shift. llvm-svn: 289429
* [X86][SSE] Regenerate vector bswap testsSimon Pilgrim2016-05-041-60/+91
| | | | llvm-svn: 268514
* [DAGCombiner] Added BSWAP(BSWAP(x)) -> x combine pattern.Simon Pilgrim2015-06-131-0/+74
| | | | llvm-svn: 239682
* [DAGCombiner] Added BSWAP vector constant folding support.Simon Pilgrim2015-06-131-3/+100
| | | | llvm-svn: 239675
* [x86] Make the new vector shuffle legality test on by default, whichChandler Carruth2015-02-201-195/+92
| | | | | | | | | | reflects the fact that the x86 backend can in fact lower any shuffle you want it to with reasonably high code quality. My recent work on the new vector shuffle has made this regress *very* little. The diff in the test cases makes me very, very happy. llvm-svn: 229958
* [x86] Clean up a couple of test cases with the new update script. SplitChandler Carruth2015-02-201-126/+343
| | | | | | | | one test case that is only partially tested in 32-bits into two test cases so that the script doesn't generate massive spews of tests for the cases we don't care about. llvm-svn: 229955
* [x86] Fix the completely broken vector widening legalization of bswap.Chandler Carruth2014-07-031-0/+29
| | | | | | | | | | | | This operation was classified as a binary operation in the widening logic for some reason (clearly, untested). It is in fact a unary operation. Add a RUN line to a test to exercise this for x86. Note that again the vector widening strategy doesn't regress anything and in one case removes a totally unecessary instruction that we couldn't avoid when promoting the element type. llvm-svn: 212257
* Legalizer: Make bswap promotion safe for vectors.Benjamin Kramer2014-05-201-0/+17
| | | | llvm-svn: 209202
* SDAG: Legalize vector BSWAP into a shuffle if the shuffle is legal but the ↵Benjamin Kramer2014-05-191-6/+114
| | | | | | | | | | bswap not. - On ARM/ARM64 we get a vrev because the shuffle matching code is really smart. We still unroll anything that's not v4i32 though. - On X86 we get a pshufb with SSSE3. Required more cleverness in isShuffleMaskLegal. - On PPC we get a vperm for v8i16 and v4i32. v2i64 is unrolled. llvm-svn: 209123
* Expand vector bswap in LegalizeVectorOpsHal Finkel2014-02-031-0/+19
ISD::BSWAP was missing from the list of node types that should be expanded element-wise. llvm-svn: 200705
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