| Commit message (Collapse) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | Put VMOVPQIto64rr in the VRPDI class. | Rafael Espindola | 2013-05-01 | 1 | -0/+10 |
| | | | | | | | Patch by Joshua Magee. llvm-svn: 180842 | ||||
| * | Teach DAG combiner to constant fold fneg of a BUILD_VECTOR of constants. | Craig Topper | 2012-09-09 | 1 | -2/+2 |
| | | | | | llvm-svn: 163483 | ||||
| * | Fix assert in LowerBUILD_VECTOR for v16i16 type on AVX. | Chad Rosier | 2011-12-15 | 1 | -0/+8 |
| | | | | | | | Patch by Elena Demikhovsky <elena.demikhovsky@intel.com>! llvm-svn: 146684 | ||||
| * | Add support for lowering fneg when AVX is enabled. | Chad Rosier | 2011-12-15 | 1 | -0/+8 |
| | | | | | | | rdar://10566486 llvm-svn: 146625 | ||||
| * | Expand V_SET0 to xorps by default. | Jakob Stoklund Olesen | 2011-11-07 | 1 | -1/+1 |
| | | | | | | | | | | The xorps instruction is smaller than pxor, so prefer that encoding. The ExecutionDepsFix pass will switch the encoding to pxor and xorpd when appropriate. llvm-svn: 143996 | ||||
| * | Change all checks regarding the presence of any SSE level to always | Bruno Cardoso Lopes | 2011-09-15 | 1 | -1/+1 |
| | | | | | | | | | | | take into consideration the presence of AVX. This change, together with the SSEDomainFix enabled for AVX, makes AVX codegen to always (hopefully) emit the same code as SSE for 128-bit vector ops. I don't have a testcase for this, but AVX now beats SSE in performance for 128-bit ops in the majority of programas in the llvm testsuite llvm-svn: 139817 | ||||
| * | Fix PR10845. SUBREG_TO_REG shouldn't be used when the input and | Bruno Cardoso Lopes | 2011-09-12 | 1 | -0/+14 |
| | | | | | | | destination types are equal! llvm-svn: 139553 | ||||
| * | Add support for 256-bit versions of VSHUFPD and VSHUFPS. | Bruno Cardoso Lopes | 2011-08-25 | 1 | -4/+2 |
| | | | | | llvm-svn: 138546 | ||||
| * | Instead of always leaving the work to the generic legalizer when | Bruno Cardoso Lopes | 2011-08-16 | 1 | -0/+43 |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | there is no support for native 256-bit shuffles, be more smart in some cases, for example, when you can extract specific 128-bit parts and use regular 128-bit shuffles for them. Example: For this shuffle: shufflevector <4 x i64> %a, <4 x i64> %b, <4 x i32> <i32 1, i32 0, i32 7, i32 6> This was expanded to: vextractf128 $1, %ymm1, %xmm2 vpextrq $0, %xmm2, %rax vmovd %rax, %xmm1 vpextrq $1, %xmm2, %rax vmovd %rax, %xmm2 vpunpcklqdq %xmm1, %xmm2, %xmm1 vpextrq $0, %xmm0, %rax vmovd %rax, %xmm2 vpextrq $1, %xmm0, %rax vmovd %rax, %xmm0 vpunpcklqdq %xmm2, %xmm0, %xmm0 vinsertf128 $1, %xmm1, %ymm0, %ymm0 ret Now we get: vshufpd $1, %xmm0, %xmm0, %xmm0 vextractf128 $1, %ymm1, %xmm1 vshufpd $1, %xmm1, %xmm1, %xmm1 vinsertf128 $1, %xmm1, %ymm0, %ymm0 llvm-svn: 137733 | ||||
| * | Fix PR10492 by teaching MOVHLPS and MOVLPS mask matching to be more strict. | Bruno Cardoso Lopes | 2011-08-11 | 1 | -0/+8 |
| | | | | | llvm-svn: 137324 | ||||
| * | Rename and tidy up tests | Bruno Cardoso Lopes | 2011-08-09 | 1 | -0/+44 |
| llvm-svn: 137103 | |||||
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index : bcm5719-llvm | |
| Project Ortega BCM5719 LLVM | Raptor Computing Systems |
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