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* [GlobalISel][X86] Split test file. NFCIgor Breger2017-05-102-42/+44
| | | | llvm-svn: 302647
* [GlobalISel][X86] G_ZEXT i1 to i32/i64 support.Igor Breger2017-05-106-1/+230
| | | | | | | | | | | | | | Summary: Support G_ZEXT i1 to i32/i64 instruction selection. Reviewers: zvi, guyblank Reviewed By: guyblank Subscribers: rovka, llvm-commits, kristof.beyls Differential Revision: https://reviews.llvm.org/D32965 llvm-svn: 302623
* [GlobalISel][X86] G_GEP selection support.Igor Breger2017-05-084-0/+306
| | | | | | | | | | | | | | Summary: [GlobalISel][X86] G_GEP selection support. Reviewers: zvi, guyblank Reviewed By: guyblank Subscribers: dberris, rovka, llvm-commits, kristof.beyls Differential Revision: https://reviews.llvm.org/D32396 llvm-svn: 302412
* [GlobalISel][X86] G_MUL legalizer/selector support.Igor Breger2017-05-0811-0/+1272
| | | | | | | | | | | | | | | | | Summary: G_MUL legalizer/selector/regbank support. Use only Tablegen-erated instruction selection. This patch dealing with legal operations only. Reviewers: zvi, guyblank Reviewed By: guyblank Subscribers: krytarowski, rovka, kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D32698 llvm-svn: 302410
* MachineFrameInfo: Track whether MaxCallFrameSize is computed yet; NFCMatthias Braun2017-05-011-1/+0
| | | | | | | | | | This tracks whether MaxCallFrameSize is computed yet. Ideally we would assert and fail when the value is queried before it is computed, however this fails various targets that need to be fixed first. Differential Revision: https://reviews.llvm.org/D32570 llvm-svn: 301851
* [GlobalISel][X86] rename test file. NFC.Igor Breger2017-05-011-0/+0
| | | | llvm-svn: 301793
* [GlobalISel][X86] G_SEXT/G_ZEXT support.Igor Breger2017-05-016-0/+576
| | | | | | | | | | | | Reviewers: zvi, guyblank Reviewed By: zvi Subscribers: rovka, llvm-commits, kristof.beyls Differential Revision: https://reviews.llvm.org/D32591 llvm-svn: 301790
* [GlobalISel][X86] G_LOAD/G_STORE pointer selection support.Igor Breger2017-05-014-0/+483
| | | | | | | | | | | | | | Summary: [GlobalISel][X86] G_LOAD/G_STORE pointer selection support. Reviewers: zvi, guyblank Reviewed By: zvi, guyblank Subscribers: dberris, rovka, kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D32217 llvm-svn: 301788
* [globalisel][tablegen] Compute available feature bits correctly.Daniel Sanders2017-04-291-0/+37
| | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: Predicate<> now has a field to indicate how often it must be recomputed. Currently, there are two frequencies, per-module (RecomputePerFunction==0) and per-function (RecomputePerFunction==1). Per-function predicates are currently recomputed more frequently than necessary since the only predicate in this category is cheap to test. Per-module predicates are now computed in getSubtargetImpl() while per-function predicates are computed in selectImpl(). Tablegen now manages the PredicateBitset internally. It should only be necessary to add the required includes. Also fixed a problem revealed by the test case where constrainSelectedInstRegOperands() would attempt to tie operands that BuildMI had already tied. Reviewers: ab, qcolombet, t.p.northover, rovka, aditya_nandakumar Reviewed By: rovka Subscribers: kristof.beyls, igorb, llvm-commits Differential Revision: https://reviews.llvm.org/D32491 llvm-svn: 301750
* [GlobalISel][X86] handle not symmetric G_COPYIgor Breger2017-04-273-0/+134
| | | | | | | | | | | | | | Summary: handle not symmetric G_COPY Reviewers: zvi, guyblank Reviewed By: guyblank Subscribers: rovka, llvm-commits, kristof.beyls Differential Revision: https://reviews.llvm.org/D32420 llvm-svn: 301523
* [X86][SSE2] Fix asm string for movq (Move Quadword) instruction.Ayman Musa2017-04-261-2/+2
| | | | | | | | Replace "mov{d|q}" with "movq". Differential Revision: https://reviews.llvm.org/D32220 llvm-svn: 301386
* [GlobalISel][X86] Lower FormalArgument/Ret using ↵Igor Breger2017-04-243-26/+145
| | | | | | | | | | | | | | | | G_MERGE_VALUES/G_UNMERGE_VALUES. Summary: [GlobalISel][X86] Lower FormalArgument/Ret using G_MERGE_VALUES/G_UNMERGE_VALUES. Reviewers: zvi, t.p.northover, guyblank Reviewed By: t.p.northover Subscribers: dberris, rovka, llvm-commits, kristof.beyls Differential Revision: https://reviews.llvm.org/D32288 llvm-svn: 301194
* [GlobalIsel][X86] support G_TRUNC selection.Igor Breger2017-04-194-0/+299
| | | | | | | | | | | | | | | | Summary: [GlobalIsel][X86] support G_TRUNC selection. Add regbank-select and legalizer tests. Currently legalization of trunc i64 on 32bit platform not supported. Reviewers: ab, zvi, rovka Reviewed By: zvi Subscribers: dberris, kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D32115 llvm-svn: 300678
* [GlobalISel][X86] Split select tests. NFC.Igor Breger2017-04-197-444/+455
| | | | llvm-svn: 300666
* [GlobalIsel][X86] support G_CONSTANT selection.Igor Breger2017-04-123-0/+224
| | | | | | | | | | | | | | Summary: [GlobalISel][X86] support G_CONSTANT selection. Add regbank select tests. Reviewers: zvi, guyblank Reviewed By: guyblank Subscribers: llvm-commits, dberris, rovka, kristof.beyls Differential Revision: https://reviews.llvm.org/D31974 llvm-svn: 300057
* [GlobalISel] implement narrowing for G_CONSTANT.Igor Breger2017-04-071-0/+43
| | | | | | | | | | | | | | Summary: [GlobalISel] implement narrowing for G_CONSTANT. Reviewers: bogner, zvi, t.p.northover Reviewed By: t.p.northover Subscribers: llvm-commits, dberris, rovka, kristof.beyls Differential Revision: https://reviews.llvm.org/D31744 llvm-svn: 299772
* [GlobalISel][X86] support G_FRAME_INDEX instruction selection.Igor Breger2017-03-283-49/+99
| | | | | | | | | | | | | | | | Summary: G_LOAD/G_STORE, add alternative RegisterBank mapping. For G_LOAD, Fast and Greedy mode choose the same RegisterBank mapping (GprRegBank ) for the G_GLOAD + G_FADD , can't get rid of cross register bank copy GprRegBank->VecRegBank. Reviewers: zvi, rovka, qcolombet, ab Reviewed By: zvi Subscribers: llvm-commits, dberris, kristof.beyls, eladcohen, guyblank Differential Revision: https://reviews.llvm.org/D30979 llvm-svn: 298907
* [GlobalISel][X86] support G_FRAME_INDEX instruction selection.Igor Breger2017-03-262-0/+66
| | | | | | | | | | | | | | | Summary: Support G_FRAME_INDEX instruction selection. Reviewers: zvi, rovka, ab, qcolombet Reviewed By: ab Subscribers: llvm-commits, dberris, kristof.beyls, eladcohen, guyblank Differential Revision: https://reviews.llvm.org/D30980 llvm-svn: 298800
* [GlobalISel][X86] Support G_STORE/G_LOAD operationIgor Breger2017-03-235-0/+1102
| | | | | | | | | | | | | | | | | | Summary: 1. Support pointer type as function argumnet and return value 2. G_STORE/G_LOAD - set legal action for i8/i16/i32/i64/f32/f64/vec128 3. RegisterBank - support typeless operations like G_STORE/G_LOAD, for scalar use GPR bank. 4. Support instruction selection for G_LOAD/G_STORE Reviewers: zvi, rovka, ab, qcolombet Reviewed By: rovka Subscribers: llvm-commits, dberris, kristof.beyls, eladcohen, guyblank Differential Revision: https://reviews.llvm.org/D30973 llvm-svn: 298609
* [GlobalISel] Don't select trivially dead instructions.Ahmed Bougacha2017-03-191-0/+4
| | | | | | | | | | | | | | Folding instructions when selecting can cause them to become dead. Don't select these dead instructions (if they don't have other side effects, and don't define physical registers). Preserve existing tests by adding COPYs. In some tests, the G_CONSTANT vregs never get constrained to a class: the only use of the vreg was folded into another instruction, so the G_CONSTANT, now dead, never gets selected. llvm-svn: 298224
* ARM: avoid clobbering register in v6 jump-table expansion.Tim Northover2017-03-151-0/+1
| | | | | | | | | | | If we got unlucky with register allocation and actual constpool placement, we could end up producing a tTBB_JT with an index that's already been clobbered. Technically, we might be able to fix this situation up with a MOV, but I think the constant islands pass is complex enough without having to deal with more weird edge-cases. llvm-svn: 297871
* GlobalISel: restrict G_EXTRACT instruction to just one operand.Tim Northover2017-03-062-11/+27
| | | | | | | A bit more painful than G_INSERT because it was more widely used, but this should simplify the handling of extract operations in most locations. llvm-svn: 297100
* [GlobalISel][X86] Support float/double and vector types.Igor Breger2017-03-036-124/+686
| | | | | | | | | | | | | | Summary: [GlobalISel][X86] Add support for f32/f64 and vector types in RegisterBank and InstructionSelector. Reviewers: delena, zvi Reviewed By: zvi Subscribers: dberris, rovka, llvm-commits, kristof.beyls Differential Revision: https://reviews.llvm.org/D30533 llvm-svn: 296856
* [X86][GlobalISel] Initial implementation , select G_ADD gpr, gprIgor Breger2017-02-223-0/+206
| | | | | | | | | | | | | | Summary: Initial implementation for X86InstructionSelector. Handle selection COPY and G_ADD/G_SUB gpr, gpr . Reviewers: qcolombet, rovka, zvi, ab Reviewed By: rovka Subscribers: mgorny, dberris, kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D29816 llvm-svn: 295824
* [X86][GlobalISel] Add general-purpose Register BankIgor Breger2017-02-102-0/+177
| | | | | | | | | | | | | | | | | Summary: [X86][GlobalISel] Add general-purpose Register Bank. Add trivial handling of G_ADD legalization . Add Regestry Bank selection for COPY and G_ADD instructions Reviewers: rovka, zvi, ab, t.p.northover, qcolombet Reviewed By: qcolombet Subscribers: qcolombet, mgorny, dberris, kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D29771 llvm-svn: 294723
* [X86][GlobalISel] Add limited ret lowering support to the IRTranslator.Igor Breger2017-02-062-38/+181
| | | | | | | | | | | | | | | | Summary: Support return lowering for i8/i16/i32/i64/float/double, vector type supported for 64bit platform only. Support argument lowering for float/double types. Reviewers: t.p.northover, zvi, ab, rovka Reviewed By: zvi Subscribers: dberris, kristof.beyls, delena, llvm-commits Differential Revision: https://reviews.llvm.org/D29261 llvm-svn: 294173
* [X86][GlobalISel] Add limited argument lowering support to the IRTranslator.Igor Breger2017-01-292-0/+163
| | | | | | | | | | | | | | | | Summary: Add limited (i8/i16/i32/i64) argument lowering support to the IRTranslator. Inspired by commit 289940. Reviewers: t.p.northover, qcolombet, ab, zvi, rovka Reviewed By: rovka Subscribers: dberris, rovka, kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D28987 llvm-svn: 293427
* [GlobalISel] Add support for address-taken basic blocksKristof Beyls2017-01-051-1/+1
| | | | | | | | | | | | | | | | | To make this work, pointers from the MachineBasicBlock to the LLVM-IR-level basic blocks need to be initialized, as the AsmPrinter uses this link to be able to print out labels for the basic blocks that are address-taken. Most of the changes in this commit are about adapting existing tests to include the basic block name that is now printed out in the MIR format, now that the name becomes available as the link to the LLVM-IR basic block is initialized. The relevant test change for the functionality added in this patch are the added "(address-taken)" strings in test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll. Differential Revision: https://reviews.llvm.org/D28123 llvm-svn: 291105
* [IRTranslator] Merge the entry and ABI lowering blocks.Quentin Colombet2016-12-151-3/+1
| | | | | | | | | | | | | | | The IRTranslator uses an additional block before the LLVM-IR entry block to perform all the ABI lowering and the constant hoisting. Thus, this block is the actual entry block and it falls through the LLVM-IR entry block. However, with such representation, we end up with two basic blocks that are not maximal. Therefore, this patch adds a bit of canonicalization by merging both the LLVM-IR entry block and the ABI lowering/constants hoisting into one block, making the resulting block more likely to be maximal (indeed the LLVM-IR entry block might not have been maximal). llvm-svn: 289891
* GlobalISel: simplify MachineIRBuilder interface.Tim Northover2016-12-071-0/+2
| | | | | | | | | | | | MachineIRBuilder had weird before/after and beginning/end flags for the insert point. Unfortunately the non-default means that instructions will be inserted in reverse order which is almost never what anyone wants. Really, I think we just want (like IRBuilder has) the ability to insert at any C++ iterator-style point (i.e. before any instruction or before MBB.end()). So this fixes MIRBuilders to behave like IRBuilders in this respect. llvm-svn: 288980
* [X86][GlobalISel] Add minimal call lowering support to the IRTranslatorZvi Rackover2016-11-152-0/+33
Summary: Add basic functionality to support call lowering for X86. Currently only supports functions which return void and take zero arguments. Inspired by commit 286573. Reviewers: ab, qcolombet, t.p.northover Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D26593 llvm-svn: 286935
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