summaryrefslogtreecommitdiffstats
path: root/llvm/test/CodeGen/Thumb
Commit message (Collapse)AuthorAgeFilesLines
...
* When getting the number of bits necessary for addressing modeBill Wendling2011-10-101-1/+1
| | | | | | | | ARMII::AddrModeT1_s, we need to take into account that if the frame register is ARM::SP, then the number of bits is 8. If it's not ARM::SP, then the number of bits is 5. llvm-svn: 141529
* Peephole optimization for ABS on ARM.Anton Korobeynikov2011-10-071-3/+8
| | | | | | Patch by Ana Pazos! llvm-svn: 141365
* Convert more tests to new atomic instructions.Eli Friedman2011-09-261-13/+1
| | | | llvm-svn: 140567
* Disable these tests harder. They're XFAIL'd, but that means they still run, andNick Lewycky2011-09-061-1/+2
| | | | | | these tests all infinitely recurse, bringing my system down into swapping hell. llvm-svn: 139192
* Revert r131152, r129796, r129761. This code is currently consideredDan Gohman2011-09-011-0/+3
| | | | | | | | to be unreliable on platforms which require memcpy calls, and it is complicating broader legalize cleanups. It is hoped that these cleanups will make memcpy byval easier to implement in the future. llvm-svn: 138977
* Change some ARM subtarget features to be single bit yes/no in order to sink ↵Evan Cheng2011-07-071-1/+1
| | | | | | them down to MC layer. Also fix tests. llvm-svn: 134590
* Add support for the 'h' constraint.Eric Christopher2011-06-301-0/+7
| | | | | | Part of rdar://9119939 llvm-svn: 134203
* rip out a ton of intrinsic modernization logic from AutoUpgrade.cpp, which isChris Lattner2011-06-181-2/+2
| | | | | | | | | for pre-2.9 bitcode files. We keep x86 unaligned loads, movnt, crc32, and the target indep prefetch change. As usual, updating the testsuite is a PITA. llvm-svn: 133337
* manually upgrade a bunch of tests to modern syntax, and remove some thatChris Lattner2011-06-172-150/+0
| | | | | | are either unreduced or only test old syntax. llvm-svn: 133228
* Don't use register classes larger than TLI->getRegClassFor(VT).Jakob Stoklund Olesen2011-06-161-0/+24
| | | | | | | | | | In Thumb mode we cannot handle GPR virtual registers, even though some instructions can. When isel is lowering a CopyFromReg, it should limit itself to subclasses of getRegClassFor(VT). <rdar://problem/9624323> llvm-svn: 133210
* FileCheck-ize test, and make it work on EABI hosts, like ↵Eli Friedman2011-06-161-7/+34
| | | | | | clang-native-arm-cortex-a9. llvm-svn: 133139
* Move this test to CodeGen/Thumb. rdar://problem/9416774Stuart Hastings2011-05-111-0/+60
| | | | llvm-svn: 131196
* Fix more register and coalescing dependencies.Jakob Stoklund Olesen2011-05-041-1/+1
| | | | llvm-svn: 130859
* Be careful about scheduling nodes above previous calls. It increase usages ofEvan Cheng2011-04-261-20/+0
| | | | | | | | | | | | more callee-saved registers and introduce copies. Only allows it if scheduling a node above calls would end up lessen register pressure. Call operands also has added ABI restrictions for register allocation, so be extra careful with hoisting them above calls. rdar://9329627 llvm-svn: 130245
* Make tests register allocation independent again.Jakob Stoklund Olesen2011-04-191-1/+1
| | | | llvm-svn: 129739
* Follow up on r127913. Fix Thumb revsh isel. rdar://9286766Evan Cheng2011-04-141-0/+56
| | | | llvm-svn: 129548
* Fix Thumb and Thumb2 tests to be register allocator independent.Jakob Stoklund Olesen2011-03-311-12/+15
| | | | llvm-svn: 128690
* Provide a legal pointer register class when targeting thumb1.Jakob Stoklund Olesen2011-03-311-1/+1
| | | | | | The LocalStackSlotAllocation pass was creating illegal registers. llvm-svn: 128687
* Roll r127459 back in:Cameron Zwarich2011-03-111-1/+1
| | | | | | | | | | | Optimize trivial branches in CodeGenPrepare, which often get created from the lowering of objectsize intrinsics. Unfortunately, a number of tests were relying on llc not optimizing trivial branches, so I had to add an option to allow them to continue to test what they originally tested. This fixes <rdar://problem/8785296> and <rdar://problem/9112893>. llvm-svn: 127498
* Revert r127459, "Optimize trivial branches in CodeGenPrepare, which often getDaniel Dunbar2011-03-111-1/+1
| | | | | | created from the", it broke some GCC test suite tests. llvm-svn: 127477
* Optimize trivial branches in CodeGenPrepare, which often get created from theCameron Zwarich2011-03-111-1/+1
| | | | | | | | | | lowering of objectsize intrinsics. Unfortunately, a number of tests were relying on llc not optimizing trivial branches, so I had to add an option to allow them to continue to test what they originally tested. This fixes <rdar://problem/8785296> and <rdar://problem/9112893>. llvm-svn: 127459
* Sorry, several patches in one.Evan Cheng2011-01-201-41/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | TargetInstrInfo: Change produceSameValue() to take MachineRegisterInfo as an optional argument. When in SSA form, targets can use it to make more aggressive equality analysis. Machine LICM: 1. Eliminate isLoadFromConstantMemory, use MI.isInvariantLoad instead. 2. Fix a bug which prevent CSE of instructions which are not re-materializable. 3. Use improved form of produceSameValue. ARM: 1. Teach ARM produceSameValue to look pass some PIC labels. 2. Look for operands from different loads of different constant pool entries which have same values. 3. Re-implement PIC GA materialization using movw + movt. Combine the pair with a "add pc" or "ldr [pc]" to form pseudo instructions. This makes it possible to re-materialize the instruction, allow machine LICM to hoist the set of instructions out of the loop and make it possible to CSE them. It's a bit hacky, but it significantly improve code quality. 4. Some minor bug fixes as well. With the fixes, using movw + movt to materialize GAs significantly outperform the load from constantpool method. 186.crafty and 255.vortex improved > 20%, 254.gap and 176.gcc ~10%. llvm-svn: 123905
* Spill R4 if it's going to be used to restore SP from FP.Evan Cheng2011-01-161-0/+17
| | | | llvm-svn: 123567
* Thumb1 had two patterns for the same load-from-constant-pool instruction.Jim Grosbach2010-12-151-3/+3
| | | | | | Canonicalize on tLDRpci and remove tLDRcp. llvm-svn: 121920
* If dbg_declare() or dbg_value() is not lowered by isel then emit DEBUG ↵Devang Patel2010-12-061-24/+19
| | | | | | message instead of creating DBG_VALUE for undefined value in reg0. llvm-svn: 121059
* Fix epilogue codegen to avoid leaving the stack pointer in an invalidEvan Cheng2010-11-222-8/+23
| | | | | | | | | | | | | | | | | state. Previously Thumb2 would restore sp from fp like this: mov sp, r7 sub, sp, #4 If an interrupt is taken after the 'mov' but before the 'sub', callee-saved registers might be clobbered by the interrupt handler. Instead, try restoring directly from sp: add sp, #4 Or, if necessary (with VLA, etc.) use a scratch register to compute sp and then restore it: sub.w r4, r7, #8 mov sp, r7 rdar://8465407 llvm-svn: 119977
* These tests are looking for library function names thatDale Johannesen2010-11-172-2/+2
| | | | | | | appear to differ on Linux. Try to make them pass on Linux. Would be good for a Linux person to review this. llvm-svn: 119572
* Do not use MEMBARRIER_MCR for any Thumb code.Bob Wilson2010-11-091-0/+1
| | | | | | | | | It is only supported for ARM code. Normally Thumb2 code would use DMB instead, but depending on how the compiler is invoked (e.g., -mattr=-db) that might be disabled. This prevents a "cannot select MEMBARRIER_MCR" error in that situation. Radar 8644195 llvm-svn: 118642
* Overhaul memory barriers in the ARM backend. Radar 8601999.Bob Wilson2010-10-301-5/+5
| | | | | | | | | | | | | | | | | | | There were a number of issues to fix up here: * The "device" argument of the llvm.memory.barrier intrinsic should be used to distinguish the "Full System" domain from the "Inner Shareable" domain. It has nothing to do with using DMB vs. DSB instructions. * The compiler should never need to emit DSB instructions. Remove the ARMISD::SYNCBARRIER node and also remove the instruction patterns for DSB. * Merge the separate DMB/DSB instructions for options only used for the disassembler with the default DMB/DSB instructions. Add the default "full system" option ARM_MB::SY to the ARM_MB::MemBOpt enum. * Add a separate ARMISD::MEMBARRIER_MCR node for subtargets that implement a data memory barrier using the MCR instruction. * Fix up encodings for these instructions (except MCR). I also updated the tests and added a few new ones to check for DMB options that were not currently being exercised. llvm-svn: 117756
* Try again to disable critical edge splitting in CodeGenPrepare.Jakob Stoklund Olesen2010-09-301-1/+1
| | | | | | The bug that broke i386 linux has been fixed in r115191. llvm-svn: 115204
* Revert "Disable codegen prepare critical edge splitting. Machine instruction ↵Jakob Stoklund Olesen2010-09-271-1/+1
| | | | | | | | | | | | | | | passes now" This reverts revision 114633. It was breaking llvm-gcc-i386-linux-selfhost. It seems there is a downstream bug that is exposed by -cgp-critical-edge-splitting=0. When that bug is fixed, this patch can go back in. Note that the changes to tailcallfp2.ll are not reverted. They were good are required. llvm-svn: 114859
* Disable codegen prepare critical edge splitting. Machine instruction passes nowEvan Cheng2010-09-231-1/+1
| | | | | | break critical edges on demand. llvm-svn: 114633
* Re-enable usage of the ARM base pointer. r113394 fixed the known failures.Jim Grosbach2010-09-081-1/+1
| | | | | | Re-running some nightly testers w/ it enabled to verify. llvm-svn: 113399
* disable for the moment while tracking down a few Thumb2-O0 failure that lookJim Grosbach2010-09-081-1/+1
| | | | | | related. (attempt deux, complete w/ test update this time) llvm-svn: 113333
* Re-apply r112883:Jim Grosbach2010-09-031-1/+1
| | | | | | | | | | | | | | "For ARM stack frames that utilize variable sized objects and have either large local stack areas or require dynamic stack realignment, allocate a base register via which to access the local frame. This allows efficient access to frame indices not accessible via the FP (either due to being out of range or due to dynamic realignment) or the SP (due to variable sized object allocation). In particular, this greatly improves efficiency of access to spill slots in Thumb functions which contain VLAs." r112986 fixed a latent bug exposed by the above. llvm-svn: 112989
* Revert "For ARM stack frames that utilize variable sized objects and have ↵Daniel Dunbar2010-09-031-1/+1
| | | | | | | | either", it is breaking oggenc with Clang for ARMv6. This reverts commit 8d6e29cfda270be483abf638850311670829ee65. llvm-svn: 112962
* For ARM stack frames that utilize variable sized objects and have eitherJim Grosbach2010-09-021-1/+1
| | | | | | | | | | | | | | | large local stack areas or require dynamic stack realignment, allocate a base register via which to access the local frame. This allows efficient access to frame indices not accessible via the FP (either due to being out of range or due to dynamic realignment) or the SP (due to variable sized object allocation). In particular, this greatly improves efficiency of access to spill slots in Thumb functions which contain VLAs. rdar://7352504 rdar://8374540 rdar://8355680 llvm-svn: 112883
* Update test for 112609Jim Grosbach2010-08-311-1/+1
| | | | llvm-svn: 112610
* Correct bogus module triple specifications.Duncan Sands2010-08-301-1/+1
| | | | llvm-svn: 112469
* Enable pre-RA virtual frame base register allocation. rdar://8277890Jim Grosbach2010-08-261-2/+2
| | | | llvm-svn: 112127
* Fix test and re-enable it.Evan Cheng2010-08-111-4/+4
| | | | llvm-svn: 110829
* Temporarily disable some failing tests, until they can beDan Gohman2010-08-111-2/+2
| | | | | | properly investigated. llvm-svn: 110808
* Add ARM Archv6M and let it implies FeatureDB (having dmb, etc.)Evan Cheng2010-08-111-6/+6
| | | | llvm-svn: 110795
* Add Cortex-M0 support. It's a ARMv6m device (no ARM mode) with some 32-bitEvan Cheng2010-08-111-5/+12
| | | | | | instructions: dmb, dsb, isb, msr, and mrs. llvm-svn: 110786
* - Add subtarget feature -mattr=+db which determine whether an ARM cpu has theEvan Cheng2010-08-111-0/+17
| | | | | | | | | memory and synchronization barrier dmb and dsb instructions. - Change instruction names to something more sensible (matching name of actual instructions). - Added tests for memory barrier codegen. llvm-svn: 110785
* Re-apply r110655 with fixes. Epilogue must restore sp from fp if the ↵Evan Cheng2010-08-101-7/+22
| | | | | | | | function stack frame has a var-sized object. Also added a test case to check for the added benefit of this patch: it's optimizing away the unnecessary restore of sp from fp for some non-leaf functions. llvm-svn: 110707
* Revert r110655, "Fix ARM hasFP() semantics. It should return true whenever FPDaniel Dunbar2010-08-101-22/+7
| | | | | | register is", it breaks a couple test-suite tests. llvm-svn: 110701
* Fix ARM hasFP() semantics. It should return true whenever FP register isEvan Cheng2010-08-101-7/+22
| | | | | | | | | | reserved, not available for general allocation. This eliminates all the extra checks for Darwin. This change also fixes the use of FP to access frame indices in leaf functions and cleaned up some confusing code in epilogue emission. llvm-svn: 110655
* Feed the right output into FileCheck.Benjamin Kramer2010-07-161-2/+2
| | | | llvm-svn: 108523
* The SelectionDAGBuilder's handling of debug info, on rareDale Johannesen2010-07-161-0/+147
| | | | | | | | | | occasions, caused code to be generated in a different order. All cases I've seen involved float softening in the type legalizer, and this could be perhaps be fixed there, but it's better not to generate things differently in the first place. 7797940 (6/29/2010..7/15/2010). llvm-svn: 108484
OpenPOWER on IntegriCloud