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* t2LEApcrel and tLEApcrel are re-materializable. This makes it possible to ↵Evan Cheng2010-05-191-6/+39
| | | | | | hoist more loads during machine LICM. llvm-svn: 104115
* Clean up the conditional for handling of sign_extend_inreg based onJim Grosbach2010-05-071-0/+22
| | | | | | | | whether the extract instructions are available. rdar://7956878 llvm-svn: 103277
* Cleanup of ARMv7M support. Move hardware divide and Thumb2 extract/packJim Grosbach2010-05-058-9/+9
| | | | | | | instructions to subtarget features and update tests to reflect. PR5717. llvm-svn: 103136
* fix copy/paste oops.Jim Grosbach2010-05-051-3/+3
| | | | llvm-svn: 103122
* Add tests for ARMV7M divide instruction useJim Grosbach2010-05-051-0/+45
| | | | llvm-svn: 103120
* Fix a bug which prevented tail merging of return instructions inDan Gohman2010-05-032-19/+16
| | | | | | | | | | | | | | | | | | | | beneficial cases. See the changes in test/CodeGen/X86/tail-opts.ll and test/CodeGen/ARM/ifcvt2.ll for details. The fix is to change HashEndOfMBB to hash at most one instruction, instead of trying to apply heuristics about when it will be profitable to consider more than one instruction. The regular tail-merging heuristics are already prepared to handle the same cases, and they're more precise. Also, make test/CodeGen/ARM/ifcvt5.ll and test/CodeGen/Thumb2/thumb2-branch.ll slightly more complex so that they continue to test what they're intended to test. And, this eliminates the problem in test/CodeGen/Thumb2/2009-10-15-ITBlockBranch.ll, the testcase from PR5204. Update it accordingly. llvm-svn: 102907
* Handle register-to-register copies within the tGPR class.Bob Wilson2010-04-261-0/+73
| | | | | | Radar 7896289 llvm-svn: 102396
* Update ARM DAGtoDAG for matching UBFX instruction for unsigned bitfieldJim Grosbach2010-04-221-0/+28
| | | | | | extraction. This fixes PR5998. llvm-svn: 102144
* - Clean up some crappy code which deals with coalescing of copies which look atEvan Cheng2010-04-211-1/+1
| | | | | | | extract_subreg / insert_subreg, etc. - Add support for more aggressive insert_subreg coalescing. llvm-svn: 101971
* Start function numbering at 0.Dan Gohman2010-04-174-10/+10
| | | | llvm-svn: 101638
* Use default lowering of DYNAMIC_STACKALLOC. As far as I can tell, ARM isle ↵Evan Cheng2010-04-151-8/+8
| | | | | | is doing the right thing and codegen looks correct for both Thumb and Thumb2. llvm-svn: 101410
* ARM SelectDYN_ALLOC should emit a copy from SP rather than referencing SP ↵Evan Cheng2010-04-151-0/+23
| | | | | | | | directly. In cases where there are two dyn_alloc in the same BB it would have caused the old SP value to be reused and badness ensues. rdar://7493908 llvm is generating poor code for dynamic alloca, I'll fix that later. llvm-svn: 101383
* switch the flag for using NEON for SP floating point to a subtarget 'feature'.Jim Grosbach2010-03-256-7/+7
| | | | | | Re-commit. This time complete with testsuite updates. llvm-svn: 99570
* Added sub-formats to the NeonI/NeonXI instructions to further refine the NEONFrmJohnny Chen2010-03-177-11/+11
| | | | | | | | | | | | | instructions to help disassembly. We also changed the output of the addressing modes to omit the '+' from the assembler syntax #+/-<imm> or +/-<Rm>. See, for example, A8.6.57/58/60. And modified test cases to not expect '+' in +reg or #+num. For example, ; CHECK: ldr.w r9, [r7, #28] llvm-svn: 98745
* --- Reverse-merging r98637 into '.':Bob Wilson2010-03-167-11/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | U test/CodeGen/ARM/tls2.ll U test/CodeGen/ARM/arm-negative-stride.ll U test/CodeGen/ARM/2009-10-30.ll U test/CodeGen/ARM/globals.ll U test/CodeGen/ARM/str_pre-2.ll U test/CodeGen/ARM/ldrd.ll U test/CodeGen/ARM/2009-10-27-double-align.ll U test/CodeGen/Thumb2/thumb2-strb.ll U test/CodeGen/Thumb2/ldr-str-imm12.ll U test/CodeGen/Thumb2/thumb2-strh.ll U test/CodeGen/Thumb2/thumb2-ldr.ll U test/CodeGen/Thumb2/thumb2-str_pre.ll U test/CodeGen/Thumb2/thumb2-str.ll U test/CodeGen/Thumb2/thumb2-ldrh.ll U utils/TableGen/TableGen.cpp U utils/TableGen/DisassemblerEmitter.cpp D utils/TableGen/RISCDisassemblerEmitter.h D utils/TableGen/RISCDisassemblerEmitter.cpp U Makefile.rules U lib/Target/ARM/ARMInstrNEON.td U lib/Target/ARM/Makefile U lib/Target/ARM/AsmPrinter/ARMInstPrinter.cpp U lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp U lib/Target/ARM/AsmPrinter/ARMInstPrinter.h D lib/Target/ARM/Disassembler U lib/Target/ARM/ARMInstrFormats.td U lib/Target/ARM/ARMAddressingModes.h U lib/Target/ARM/Thumb2ITBlockPass.cpp llvm-svn: 98640
* Initial ARM/Thumb disassembler check-in. It consists of a tablgen backendJohnny Chen2010-03-167-11/+11
| | | | | | | | | | | | | | | | | | (RISCDisassemblerEmitter) which emits the decoder functions for ARM and Thumb, and the disassembler core which invokes the decoder function and builds up the MCInst based on the decoded Opcode. Added sub-formats to the NeonI/NeonXI instructions to further refine the NEONFrm instructions to help disassembly. We also changed the output of the addressing modes to omit the '+' from the assembler syntax #+/-<imm> or +/-<Rm>. See, for example, A8.6.57/58/60. And modified test cases to not expect '+' in +reg or #+num. For example, ; CHECK: ldr.w r9, [r7, #28] llvm-svn: 98637
* Stop using the old pre-UAL syntax for LDM/STM instruction suffixes.Bob Wilson2010-03-162-3/+3
| | | | | | | This does not move entirely to UAL syntax, since the default "increment after" suffix is empty but we still use "IA" for that. llvm-svn: 98635
* Add a testcase for the change in r98586.Bob Wilson2010-03-161-0/+63
| | | | llvm-svn: 98610
* Enable machine cse pass.Evan Cheng2010-03-101-4/+2
| | | | llvm-svn: 98132
* Fix a crash compiling 254.gap for Thumb2. The Thumb2 add/sub with 12-bitBob Wilson2010-03-081-0/+266
| | | | | | | | immediate instructions cannot set the condition codes, so they do not have the extra cc_out operand. We hit an assertion during tail duplication because the instruction being duplicated had more operands that expected. llvm-svn: 98001
* Drop the ".w" qualifier for t2UXTB16* instructions as there is no 16-bit versionJohnny Chen2010-03-041-10/+10
| | | | | | of either sxtb16 or uxtb16, and the unified syntax does not specify ".w". llvm-svn: 97760
* Create a stack frame on ARM whenJakob Stoklund Olesen2010-02-241-0/+15
| | | | | | | | | | | - Function uses all scratch registers AND - Function does not use any callee saved registers AND - Stack size is too big to address with immediate offsets. In this case a register must be scavenged to calculate the address of a stack object, and the scavenger needs a spare register or emergency spill slot. llvm-svn: 97071
* LowerCall() should always do getCopyFromReg() to reference the stack pointer.Jim Grosbach2010-02-241-1/+1
| | | | | | | Machine instruction selection is much happier when operands are in virtual registers. llvm-svn: 97012
* Last week we were generating code with duplicate induction variables in thisBob Wilson2010-02-151-0/+4
| | | | | | | test, but the problem seems to have gone away today. Add a check to make sure it doesn't come back. llvm-svn: 96277
* Besides removing phi cycles that reduce to a single value, also remove deadBob Wilson2010-02-132-2/+40
| | | | | | | | phi cycles. Adjust a few tests to keep dead instructions from being optimized away. This (together with my previous change for phi cycles) fixes Apple radar 7627077. llvm-svn: 96057
* Reapply the new LoopStrengthReduction code, with compile time andDan Gohman2010-02-122-13/+17
| | | | | | | | | | bug fixes, and with improved heuristics for analyzing foreign-loop addrecs. This change also flattens IVUsers, eliminating the stride-oriented groupings, which makes it easier to work with. llvm-svn: 95975
* Add a new pass on machine instructions to optimize away PHI cycles that Bob Wilson2010-02-121-0/+34
| | | | | | | | | | | reduce down to a single value. InstCombine already does this transformation but DAG legalization may introduce new opportunities. This has turned out to be important for ARM where 64-bit values are split up during type legalization: InstCombine is not able to remove the PHI cycles on the 64-bit values but the separate 32-bit values can be optimized. I measured the compile time impact of this (running llc on 176.gcc) and it was not significant. llvm-svn: 95951
* Reapply coalescer fix for better cross-class coalescing.Jakob Stoklund Olesen2010-02-111-1/+1
| | | | | | This time with fixed test cases. llvm-svn: 95938
* Handle AddrMode6 (for NEON load/stores) in Thumb2's rewriteT2FrameIndex.Bob Wilson2010-02-061-2/+2
| | | | | | Radar 7614112. llvm-svn: 95456
* Revert LoopStrengthReduce.cpp to pre-r94061 for now.Dan Gohman2010-01-222-17/+13
| | | | llvm-svn: 94123
* Re-implement the main strength-reduction portion of LoopStrengthReduction.Dan Gohman2010-01-212-13/+17
| | | | | | | | | | | | | | This new version is much more aggressive about doing "full" reduction in cases where it reduces register pressure, and also more aggressive about rewriting induction variables to count down (or up) to zero when doing so reduces register pressure. It currently uses fairly simplistic algorithms for finding reuse opportunities, but it introduces a new framework allows it to combine multiple strategies at once to form hybrid solutions, instead of doing all full-reduction or all base+index. llvm-svn: 94061
* Remove predicates when changing an add into an unpredicable mov.Jakob Stoklund Olesen2010-01-191-0/+53
| | | | | | | Since the mov is executed unconditionally, make sure that the add didn't have any predicate. llvm-svn: 93909
* Run the pre-register allocation tail duplication pass by default. RemoveBob Wilson2010-01-161-1/+1
| | | | | | | the -pre-regalloc-taildup command-line option, and add a new -disable-early-taildup option. llvm-svn: 93597
* Add comments.Jakob Stoklund Olesen2010-01-071-0/+2
| | | | llvm-svn: 92883
* Add Target hook to duplicate machine instructions.Jakob Stoklund Olesen2010-01-061-0/+87
| | | | | | | Some instructions refer to unique labels, and so cannot be trivially cloned with CloneMachineInstr. llvm-svn: 92873
* Delete useless trailing semicolons.Dan Gohman2010-01-051-8/+8
| | | | llvm-svn: 92740
* Make this test pass on Linux.Nick Lewycky2009-12-161-9/+20
| | | | llvm-svn: 91521
* Dynamic stack realignment use of sp register as source/dest registerAnton Korobeynikov2009-12-062-2/+2
| | | | | | | | | | in "bic sp, sp, #15" leads to unpredicatble behaviour in Thumb2 mode. Emit the following code instead: mov r4, sp bic r4, r4, #15 mov sp, r4 llvm-svn: 90724
* test case for IV-Users simplification loop improvementJim Grosbach2009-12-011-0/+128
| | | | llvm-svn: 90260
* Enable predication of NEON instructions in Thumb2 mode.Evan Cheng2009-11-241-0/+29
| | | | llvm-svn: 89748
* move fconst[sd] to UAL. <rdar://7414913>Jim Grosbach2009-11-231-1/+1
| | | | llvm-svn: 89700
* update test for 89694Jim Grosbach2009-11-231-2/+2
| | | | llvm-svn: 89695
* Miss two, PR5307.Edward O'Callaghan2009-11-222-6/+30
| | | | llvm-svn: 89596
* Convert Thumb2 tests to FileCheck for PR5307.Edward O'Callaghan2009-11-2212-26/+130
| | | | llvm-svn: 89595
* Revert 89562. We're being sneakier than I was giving us credit for, and thisJim Grosbach2009-11-212-2/+0
| | | | | | isn't necessary. llvm-svn: 89568
* Darwin requires a frame pointer for all non-leaf functions to support correctJim Grosbach2009-11-212-0/+2
| | | | | | backtraces. llvm-svn: 89562
* Enable hoisting load from constant memories.Evan Cheng2009-11-201-2/+6
| | | | llvm-svn: 89510
* Remat VLDRD from constpool. Clean up some instruction property specifications.Evan Cheng2009-11-202-4/+2
| | | | llvm-svn: 89478
* Also CSE non-pic load from constant pools.Evan Cheng2009-11-201-2/+11
| | | | llvm-svn: 89440
* More consistent thumb1 asm printing.Evan Cheng2009-11-193-5/+5
| | | | llvm-svn: 89328
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