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* ARM target code clean up. Check for iOS, not Darwin where it makes sense.Evan Cheng2011-12-201-1/+1
| | | | llvm-svn: 146981
* Fix a CPSR liveness tracking bug introduced when I converted IT block to bundle.Evan Cheng2011-12-171-0/+28
| | | | llvm-svn: 146805
* Fix off-by-one error in bucket sort.Jakob Stoklund Olesen2011-12-161-0/+26
| | | | | | | | | The bad sorting caused a misaligned basic block when building 176.vpr in ARM mode. <rdar://problem/10594653> llvm-svn: 146767
* - Add MachineInstrBundle.h and MachineInstrBundle.cpp. This includes a functionEvan Cheng2011-12-142-2/+2
| | | | | | | | | | to finalize MI bundles (i.e. add BUNDLE instruction and computing register def and use lists of the BUNDLE instruction) and a pass to unpack bundles. - Teach more of MachineBasic and MachineInstr methods to be bundle aware. - Switch Thumb2 IT block to MI bundles and delete the hazard recognizer hack to prevent IT blocks from being broken apart. llvm-svn: 146542
* Manually upgrade the test suite to specify the flag to cttz and ctlz.Chandler Carruth2011-12-121-2/+2
| | | | | | | | | | | | | | | | | | | | | | | I followed three heuristics for deciding whether to set 'true' or 'false': - Everything target independent got 'true' as that is the expected common output of the GCC builtins. - If the target arch only has one way of implementing this operation, set the flag in the way that exercises the most of codegen. For most architectures this is also the likely path from a GCC builtin, with 'true' being set. It will (eventually) require lowering away that difference, and then lowering to the architecture's operation. - Otherwise, set the flag differently dependending on which target operation should be tested. Let me know if anyone has any issue with this pattern or would like specific tests of another form. This should allow the x86 codegen to just iteratively improve as I teach the backend how to differentiate between the two forms, and everything else should remain exactly the same. llvm-svn: 146370
* Teach SelectionDAG to match more calls to libm functions onto existing ↵Owen Anderson2011-12-081-2/+2
| | | | | | SDNodes. Mark these nodes as illegal by default, unless the target declares otherwise. llvm-svn: 146171
* Upgrade syntax of tests using volatile instructions to use 'load volatile' ↵Chris Lattner2011-11-271-2/+2
| | | | | | instead of 'volatile load', which is archaic. llvm-svn: 145171
* Add vmov.f32 to materialize f32 immediate splats which cannot be handled byEvan Cheng2011-11-151-3/+2
| | | | | | integer variants. rdar://10437054 llvm-svn: 144608
* ARM VLDR/VSTR instructions don't need a size suffix.Jim Grosbach2011-11-142-2/+2
| | | | | | | Canonicallize on the non-suffixed form, but continue to accept assembly that has any correctly sized type suffix. llvm-svn: 144583
* Linear scan is going away.Jakob Stoklund Olesen2011-11-121-5/+5
| | | | llvm-svn: 144472
* Switch a few tests off linearscan.Jakob Stoklund Olesen2011-11-121-2/+3
| | | | llvm-svn: 144460
* ARM Darwin default relocation model is PIC.Jim Grosbach2011-09-301-1/+1
| | | | | | | This matches clang, so default options in llc and friends are now closer to clang's defaults. llvm-svn: 140863
* Last batch of test conversions to new atomic instructions.Eli Friedman2011-09-271-31/+0
| | | | llvm-svn: 140585
* Convert more tests to new atomic instructions.Eli Friedman2011-09-262-22/+18
| | | | llvm-svn: 140567
* Generalize this test's CHECK statements to handle different indvars modes.Andrew Trick2011-09-131-2/+2
| | | | llvm-svn: 139577
* Change ARM / Thumb2 addc / adde and subc / sube modeling to use physicalEvan Cheng2011-08-301-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | register dependency (rather than glue them together). This is general goodness as it gives scheduler more freedom. However it is motivated by a nasty bug in isel. When a i64 sub is expanded to subc + sube. libcall #1 \ \ subc \ / \ \ / \ \ / libcall #2 sube If the libcalls are not serialized (i.e. both have chains which are dag entry), legalizer can serialize them in arbitrary orders. If it's unlucky, it can force libcall #2 before libcall #1 in the above case. subc | libcall #2 | libcall #1 | sube However since subc and sube are "glued" together, this ends up being a cycle when the scheduler combine subc and sube as a single scheduling unit. The right solution is to fix LegalizeType too chains the libcalls together. However, LegalizeType is not processing nodes in order so that's harder than it should be. For now, the move to physical register dependency will do. rdar://10019576 llvm-svn: 138791
* Update tests.Jim Grosbach2011-08-192-2/+2
| | | | llvm-svn: 138116
* Thumb assembly parsing and encoding for LDM instruction.Jim Grosbach2011-08-181-1/+1
| | | | | | | | Fix base register type and canonicallize to the "ldm" spelling rather than "ldmia." Add diagnostics for incorrect writeback token and out-of-range registers. llvm-svn: 137986
* Fix up the patterns for SXTB, SXTH, UXTB, and UXTH so that they are ↵Eli Friedman2011-08-081-0/+29
| | | | | | correctly active without HasT2ExtractPack. PR10611. llvm-svn: 137061
* Use MachineBranchProbabilityInfo in If-Conversion instead of its own heuristics.Jakub Staszak2011-08-032-13/+13
| | | | llvm-svn: 136826
* Introduce MCCodeGenInfo, which keeps information that can affect codegenEvan Cheng2011-07-191-1/+0
| | | | | | | (including compilation, assembly). Move relocation model Reloc::Model from TargetMachine to MCCodeGenInfo so it's accessible even without TargetMachine. llvm-svn: 135468
* Improve codegen for select's:Evan Cheng2011-07-134-115/+0
| | | | | | | | | | | | | | | | | | | | if (x != 0) x = 1 if (x == 1) x = 1 Previous codegen looks like this: mov r1, r0 cmp r1, #1 mov r0, #0 moveq r0, #1 The naive lowering select between two different values. It should recognize the test is equality test so it's more a conditional move rather than a select: cmp r0, #1 movne r0, #0 rdar://9758317 llvm-svn: 135017
* Improve test cases from r134746.Jim Grosbach2011-07-122-5/+21
| | | | | | | Use memory barriers to force if-conversion off for these tests instead of the internal llc command line option ifcvt-limit. llvm-svn: 134986
* Make tBX_RET and tBX_RET_vararg predicable.Jim Grosbach2011-07-084-9/+14
| | | | | | | | | | The normal tBX instruction is predicable, so there's no reason the pseudos for using it as a return shouldn't be. Gives us some nice code-gen improvements as can be seen by the test changes. In particular, several tests now have to disable if-conversion because it works too well and defeats the test. llvm-svn: 134746
* Fix more register allocation sensitive tests.Jakob Stoklund Olesen2011-07-083-8/+8
| | | | llvm-svn: 134667
* Change some ARM subtarget features to be single bit yes/no in order to sink ↵Evan Cheng2011-07-072-2/+2
| | | | | | them down to MC layer. Also fix tests. llvm-svn: 134590
* FileCheck-ize another test. Reduces the llc invocations from 8 to 1, andChandler Carruth2011-07-021-8/+41
| | | | | | | makes one of the tests actually mean something (as the string 'add' will always appear in the output of this file). llvm-svn: 134358
* ARMv7M vs. ARMv7E-M support.Jim Grosbach2011-07-013-4/+7
| | | | | | | | | | | | | | The DSP instructions in the Thumb2 instruction set are an optional extension in the Cortex-M* archtitecture. When present, the implementation is considered an "ARMv7E-M implementation," and when not, an "ARMv7-M implementation." Add a subtarget feature hook for the v7e-m instructions and hook it up. The cortex-m3 cpu is an example of a v7m implementation, while the cortex-m4 is a v7e-m implementation. rdar://9572992 llvm-svn: 134261
* Thumb1 register to register MOV instruction is predicable.Jim Grosbach2011-06-302-8/+7
| | | | | | | | | Fix a FIXME and allow predication (in Thumb2) for the T1 register to register MOV instructions. This allows some better codegen with if-conversion (as seen in the test updates), plus it lays the groundwork for pseudo-izing the tMOVCC instructions. llvm-svn: 134197
* Pseudo-ize the t2LDMIA_RET instruction.Jim Grosbach2011-06-301-1/+1
| | | | | | | | It's just a t2LDMIA_UPD instruction with extra codegen properties, so it doesn't need the encoding information. As a side-benefit, we now correctly recognize for instruction printing as a 'pop' instruction. llvm-svn: 134173
* Don't depend on the optimization reverted in r134067.Benjamin Kramer2011-06-291-1/+0
| | | | llvm-svn: 134068
* Remove support for parsing the "type i32" syntax for defining a numberedChris Lattner2011-06-193-16/+16
| | | | | | | top level type without a specified number. This syntax isn't documented and blocks forward progress. llvm-svn: 133371
* rip out a ton of intrinsic modernization logic from AutoUpgrade.cpp, which isChris Lattner2011-06-181-3/+2
| | | | | | | | | for pre-2.9 bitcode files. We keep x86 unaligned loads, movnt, crc32, and the target indep prefetch change. As usual, updating the testsuite is a PITA. llvm-svn: 133337
* Switch ARM to using AltOrders instead of MethodBodies.Jakob Stoklund Olesen2011-06-181-1/+1
| | | | | | | | | This slightly changes the GPR allocation order on Darwin where R9 is not a callee-saved register: Before: %R0 %R1 %R2 %R3 %R12 %R9 %LR %R4 %R5 %R6 %R8 %R10 %R11 After: %R0 %R1 %R2 %R3 %R9 %R12 %LR %R4 %R5 %R6 %R8 %R10 %R11 llvm-svn: 133326
* manually upgrade a bunch of tests to modern syntax, and remove some thatChris Lattner2011-06-172-5/+5
| | | | | | are either unreduced or only test old syntax. llvm-svn: 133228
* Implement Jakob's suggestion on how to detect fall thought without callingRafael Espindola2011-06-141-2/+2
| | | | | | AnalyzeBranch. llvm-svn: 132981
* AnalyzeBranch doesn't change which successors a bb has, just the orderRafael Espindola2011-06-121-2/+2
| | | | | | | | | | | | | | | | | | we try to branch to them. Before we were creating successor lists with duplicated entries. Fixing that found a bug in isBlockOnlyReachableByFallthrough that would causes it to return the wrong answer for ----------- ... jne foo jmp bar foo: ---------- llvm-svn: 132882
* Fix an issue where the two-address conversion pass incorrectly rewrites untiedCameron Zwarich2011-06-071-0/+36
| | | | | | operands to an early clobber register. This fixes <rdar://problem/9566076>. llvm-svn: 132738
* Switch AllocationOrder to using RegisterClassInfo instead of a BitVectorJakob Stoklund Olesen2011-06-031-1/+1
| | | | | | | | | of reserved registers. Use RegisterClassInfo in RABasic as well. This slightly changes som allocation orders because RegisterClassInfo puts CSR aliases last. llvm-svn: 132581
* Since I can't reproduce the failures from 131261, re-trying with aStuart Hastings2011-05-131-7/+10
| | | | | | simplified version. <rdar://problem/9298790> llvm-svn: 131274
* Revert 131266 and 131261 due to buildbot complaints.Stuart Hastings2011-05-131-10/+7
| | | | | | rdar://problem/9298790 llvm-svn: 131269
* Tweak 131261 (thumb2-cbnz.ll) to generate the intended cbnz.Stuart Hastings2011-05-131-8/+10
| | | | | | rdar://problem/9298790 llvm-svn: 131266
* Non-fast-isel followup to 129634; correctly handle branches controlledStuart Hastings2011-05-121-3/+4
| | | | | | | | | | | | | by non-CMP expressions. The executable test case (129821) would test this as well, if we had an "-O0 -disable-arm-fast-isel" LLVM-GCC tester. Alas, the ARM assembly would be very difficult to check with FileCheck. The thumb2-cbnz.ll test is affected; it generates larger code (tst.w vs. cmp #0), but I believe the new version is correct. rdar://problem/9298790 llvm-svn: 131261
* Re-revert r130877; it's apparently causing a regression on 197.parser,Eli Friedman2011-05-061-2/+2
| | | | | | possibly related to cbnz formation. llvm-svn: 130977
* Re-commit r130862 with a minor change to avoid an iterator running off the ↵Eli Friedman2011-05-041-2/+2
| | | | | | | | | | edge in some cases. Original message: Teach MachineCSE how to do simple cross-block CSE involving physregs. This allows, for example, eliminating duplicate cmpl's on x86. Part of rdar://problem/8259436 . llvm-svn: 130877
* Back out r130862; it appears to be breaking bootstrap.Eli Friedman2011-05-041-2/+2
| | | | llvm-svn: 130867
* Teach MachineCSE how to do simple cross-block CSE involving physregs. This ↵Eli Friedman2011-05-041-2/+2
| | | | | | allows, for example, eliminating duplicate cmpl's on x86. Part of rdar://problem/8259436 . llvm-svn: 130862
* Fix more register and coalescing dependencies.Jakob Stoklund Olesen2011-05-042-7/+6
| | | | llvm-svn: 130859
* Explicitly request physreg coalesing for a bunch of Thumb2 unit tests.Jakob Stoklund Olesen2011-05-047-7/+26
| | | | | | | | | | | | | | | | | | | | | | | | | | | These tests all follow the same pattern: mov r2, r0 movs r0, #0 $CMP r2, r1 it eq moveq r0, #1 bx lr The first 'mov' can be eliminated by rematerializing 'movs r0, #0' below the test instruction: $CMP r0, r1 mov.w r0, #0 it eq moveq r0, #1 bx lr So far, only physreg coalescing can do that. The register allocators won't yet split live ranges just to eliminate copies. They can learn, but this particular problem is not likely to show up in real code. It only appears because r0 is used for both the function argument and return value. llvm-svn: 130858
* Weekly fix of register allocation dependent unit tests.Jakob Stoklund Olesen2011-04-301-10/+10
| | | | llvm-svn: 130567
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