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* Mass update to CodeGen tests to use CHECK-LABEL for labels corresponding to ↵Stephen Lin2013-07-141-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | function definitions for more informative error messages. No functionality change and all updated tests passed locally. This update was done with the following bash script: find test/CodeGen -name "*.ll" | \ while read NAME; do echo "$NAME" if ! grep -q "^; *RUN: *llc.*debug" $NAME; then TEMP=`mktemp -t temp` cp $NAME $TEMP sed -n "s/^define [^@]*@\([A-Za-z0-9_]*\)(.*$/\1/p" < $NAME | \ while read FUNC; do sed -i '' "s/;\(.*\)\([A-Za-z0-9_-]*\):\( *\)$FUNC: *\$/;\1\2-LABEL:\3$FUNC:/g" $TEMP done sed -i '' "s/;\(.*\)-LABEL-LABEL:/;\1-LABEL:/" $TEMP sed -i '' "s/;\(.*\)-NEXT-LABEL:/;\1-NEXT:/" $TEMP sed -i '' "s/;\(.*\)-NOT-LABEL:/;\1-NOT:/" $TEMP sed -i '' "s/;\(.*\)-DAG-LABEL:/;\1-DAG:/" $TEMP mv $TEMP $NAME fi done llvm-svn: 186280
* Pseudo-ize the t2LDMIA_RET instruction.Jim Grosbach2011-06-301-1/+1
| | | | | | | | It's just a t2LDMIA_UPD instruction with extra codegen properties, so it doesn't need the encoding information. As a side-benefit, we now correctly recognize for instruction printing as a 'pop' instruction. llvm-svn: 134173
* Switch AllocationOrder to using RegisterClassInfo instead of a BitVectorJakob Stoklund Olesen2011-06-031-1/+1
| | | | | | | | | of reserved registers. Use RegisterClassInfo in RABasic as well. This slightly changes som allocation orders because RegisterClassInfo puts CSR aliases last. llvm-svn: 132581
* Be careful about scheduling nodes above previous calls. It increase usages ofEvan Cheng2011-04-261-1/+1
| | | | | | | | | | | | more callee-saved registers and introduce copies. Only allows it if scheduling a node above calls would end up lessen register pressure. Call operands also has added ABI restrictions for register allocation, so be extra careful with hoisting them above calls. rdar://9329627 llvm-svn: 130245
* Fix Thumb and Thumb2 tests to be register allocator independent.Jakob Stoklund Olesen2011-03-311-1/+2
| | | | llvm-svn: 128690
* Now that register allocation properly considers reserved regs, simplify theJim Grosbach2010-09-021-2/+2
| | | | | | ARM register class allocation order functions to take advantage of that. llvm-svn: 112841
* Fix test to appease the buildbots.Bob Wilson2010-07-141-1/+1
| | | | llvm-svn: 108334
* Fix an inverted condition.Evan Cheng2010-06-181-2/+0
| | | | llvm-svn: 106330
* Make post-ra scheduling, anti-dep breaking, and register scavenger ↵Evan Cheng2010-06-161-0/+2
| | | | | | (conservatively) aware of predicated instructions. This enables ARM to move if-conversion before post-ra scheduler. llvm-svn: 106091
* Fix a bug which prevented tail merging of return instructions inDan Gohman2010-05-031-7/+4
| | | | | | | | | | | | | | | | | | | | beneficial cases. See the changes in test/CodeGen/X86/tail-opts.ll and test/CodeGen/ARM/ifcvt2.ll for details. The fix is to change HashEndOfMBB to hash at most one instruction, instead of trying to apply heuristics about when it will be profitable to consider more than one instruction. The regular tail-merging heuristics are already prepared to handle the same cases, and they're more precise. Also, make test/CodeGen/ARM/ifcvt5.ll and test/CodeGen/Thumb2/thumb2-branch.ll slightly more complex so that they continue to test what they're intended to test. And, this eliminates the problem in test/CodeGen/Thumb2/2009-10-15-ITBlockBranch.ll, the testcase from PR5204. Update it accordingly. llvm-svn: 102907
* Stop using the old pre-UAL syntax for LDM/STM instruction suffixes.Bob Wilson2010-03-161-2/+2
| | | | | | | This does not move entirely to UAL syntax, since the default "increment after" suffix is empty but we still use "IA" for that. llvm-svn: 98635
* Branches must be the last instruction in a Thumb2 IT block. Approved by Evan ↵Sandeep Patel2009-10-151-0/+44
Cheng. llvm-svn: 84212
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