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* Pythran compat - range vs. xrangeSerge Guelton2019-01-031-3/+3
| | | | | | | | | Use range instead of xrange whenever possible. The extra list creation in Python2 is generally not a performance bottleneck. Differential Revision: https://reviews.llvm.org/D56253 llvm-svn: 350309
* Python compat - print statementSerge Guelton2019-01-031-25/+27
| | | | | | | | | Make sure all print statements are compatible with Python 2 and Python3 using the `from __future__ import print_function` statement. Differential Revision: https://reviews.llvm.org/D56249 llvm-svn: 350307
* [SystemZ] Fix large tests broken by conditional returns.Marcin Koscielnicki2016-04-151-0/+3
| | | | | | | | These were broken by D17339. Differential Revision: http://reviews.llvm.org/D19158 llvm-svn: 266454
* Update SystemZ/Large test generators to handle new gep IR syntaxDavid Blaikie2015-02-271-3/+3
| | | | llvm-svn: 230810
* Update SystemZ/Large test generators to handle new load IR syntaxDavid Blaikie2015-02-271-2/+2
| | | | llvm-svn: 230809
* Add TargetLowering::prepareVolatileOrAtomicLoadRichard Sandiford2013-12-101-2/+2
| | | | | | | | | | | | | | | | | One unusual feature of the z architecture is that the result of a previous load can be reused indefinitely for subsequent loads, even if a cache-coherent store to that location is performed by another CPU. A special serializing instruction must be used if you want to force a load to be reattempted. Since volatile loads are not supposed to be omitted in this way, we should insert a serializing instruction before each such load. The same goes for atomic loads. The patch implements this at the IR->DAG boundary, in a similar way to atomic fences. It is a no-op for targets other than SystemZ. llvm-svn: 196905
* [SystemZ] Register compare-and-branch supportRichard Sandiford2013-05-281-0/+111
This patch adds support for the CRJ and CGRJ instructions. Support for the immediate forms will be a separate patch. The architecture has a large number of comparison instructions. I think it's generally better to concentrate on using the "best" comparison instruction first and foremost, then only use something like CRJ if CR really was the natual choice of comparison instruction. The patch therefore opportunistically converts separate CR and BRC instructions into a single CRJ while emitting instructions in ISelLowering. llvm-svn: 182764
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