summaryrefslogtreecommitdiffstats
path: root/llvm/test/CodeGen/RISCV
Commit message (Collapse)AuthorAgeFilesLines
...
* [RISCV] Implement codegen for cmpxchg on RV32IAAlex Bradbury2018-11-291-0/+769
| | | | | | | | | | | | | Utilise a similar ('late') lowering strategy to D47882. The changes to AtomicExpandPass allow this strategy to be utilised by other targets which implement shouldExpandAtomicCmpXchgInIR. All cmpxchg are lowered as 'strong' currently and failure ordering is ignored. This is conservative but correct. Differential Revision: https://reviews.llvm.org/D48131 llvm-svn: 347914
* [RISCV] Constant materialisation for RV64IAlex Bradbury2018-11-161-7/+204
| | | | | | | | | | | | | | | | | | | | | | | This commit introduces support for materialising 64-bit constants for RV64I, making use of the RISCVMatInt::generateInstSeq helper in order to share logic for immediate materialisation with the MC layer (where it's used for the li pseudoinstruction). test/CodeGen/RISCV/imm.ll is updated to test RV64, and gains new 64-bit constant tests. It would be preferable if anyext constant returns were sign rather than zero extended (see PR39092). This patch simply adds an explicit signext to the returns in imm.ll. Further optimisations for constant materialisation are possible, most notably for mask-like values which can be generated my loading -1 and shifting right. A future patch will standardise on the C++ codepath for immediate selection on RV32 as well as RV64, and then add further such optimisations to RISCVMatInt::generateInstSeq in order to benefit both RV32 and RV64 for codegen and li expansion. Differential Revision: https://reviews.llvm.org/D52962 llvm-svn: 347042
* [RISCV] Mark FREM as ExpandAlex Bradbury2018-11-152-0/+32
| | | | | | | | | | | | Mark the FREM SelectionDAG node as Expand, which is necessary in order to support the frem IR instruction on RISC-V. This is expanded into a library call. Adds the corresponding test. Previously, this would have triggered an assertion at instruction selection time. Differential Revision: https://reviews.llvm.org/D54159 Patch by Luís Marques. llvm-svn: 346958
* [RISCV] Support .option relax and .option norelaxAlex Bradbury2018-11-123-0/+52
| | | | | | | | | | | | | | | | | | | | | | This extends the .option support from D45864 to enable/disable the relax feature flag from D44886 During parsing of the relax/norelax directives, the RISCV::FeatureRelax feature bits of the SubtargetInfo stored in the AsmParser are updated appropriately to reflect whether relaxation is currently enabled in the parser. When an instruction is parsed, the parser checks if relaxation is currently enabled and if so, gets a handle to the AsmBackend and sets the ForceRelocs flag. The AsmBackend uses a combination of the original RISCV::FeatureRelax feature bits set by e.g -mattr=+/-relax and the ForceRelocs flag to determine whether to emit relocations for symbol and branch diffs. Diff relocations should therefore only not be emitted if the relax flag was not set on the command line and no instruction was ever parsed in a section with relaxation enabled to ensure correct diffs are emitted. Differential Revision: https://reviews.llvm.org/D46423 Patch by Lewis Revill. llvm-svn: 346655
* [RISCV] Avoid unnecessary XOR for seteq/setne 0Alex Bradbury2018-11-095-115/+114
| | | | | | | | Differential Revision: https://reviews.llvm.org/D53492 Patch by James Clarke. llvm-svn: 346497
* [RISCV] Update test/CodeGen/RISCV/calling-conv.ll after rL346432Alex Bradbury2018-11-091-8/+8
| | | | | | The DAGCombiner changes led to a different schedule. llvm-svn: 346496
* [RISCV] Add some missing expansions for floating-point intrinsicsAlex Bradbury2018-11-022-7/+750
| | | | | | | | | | | | | | | | | | A number of intrinsics, such as llvm.sin.f32, would result in a failure to select. This patch adds expansions for the relevant selection DAG nodes, as well as exhaustive testing for all f32 and f64 intrinsics. The codegen for FMA remains a TODO item, pending support for the various RISC-V FMA instruction variants. The llvm.minimum.f32.* and llvm.maximum.* tests are commented-out, pending upstream support for target-independent expansion, as discussed in http://lists.llvm.org/pipermail/llvm-dev/2018-November/127408.html. Differential Revision: https://reviews.llvm.org/D54034 Patch by Luís Marques. llvm-svn: 346034
* [RISCV] Eliminate unnecessary masking of promoted shift amountsAlex Bradbury2018-10-123-14/+70
| | | | | | | | | | | | | | | | SelectionDAGBuilder::visitShift will always zero-extend a shift amount when it is promoted to the ShiftAmountTy. This results in zero-extension (masking) which is unnecessary for RISC-V as the shift operations only read the lower 5 or 6 bits (RV32 or RV64). I initially proposed adding a getExtendForShiftAmount hook so the shift amount can be any-extended (D52975). @efriedma explained this was unsafe, so I have instead eliminate the unnecessary and operations at instruction selection time in a manner similar to X86InstrCompiler.td. Differential Revision: https://reviews.llvm.org/D53224 llvm-svn: 344432
* [RISCV] Re-generate test/CodeGen/RISCV/vararg.ll after r344142Alex Bradbury2018-10-111-34/+32
| | | | | | The improved load-store forwarding committed in r344142 broke this test. llvm-svn: 344238
* [RISCV] Update alu8.ll and alu16.ll test casesAlex Bradbury2018-10-082-5/+9
| | | | | | | | The srli test in alu8.ll was a no-op, as it shifted by 8 bits. Fix this, and also change the immediate in alu16.ll as shifted by something other than a poewr of 8 is more interesting. llvm-svn: 343958
* [RISCV] Introduce alu8.ll and alu16.ll testsAlex Bradbury2018-10-072-0/+412
| | | | | | | These track the quality of generated code for simple arithmetic operations that were legalised from non-native types. llvm-svn: 343930
* [RISCV] Regenerate several tests now enableMultipleCopyHints is enabled by ↵Alex Bradbury2018-10-053-60/+60
| | | | | | | | default r343851 caused codegen changes in several tests. This patch regenerates them. llvm-svn: 343873
* [RISCV][NFC] Remove dead CHECK lines from vararg.ll testAlex Bradbury2018-10-041-310/+0
| | | | | | The RISCV32 check prefix is no longer used so these lines are dead. llvm-svn: 343757
* [RISCV] Bugfix for floats passed on the stack with the ILP32 ABI on RV32FAlex Bradbury2018-10-041-0/+81
| | | | | | | | | | | | | f32 values passed on the stack would previously cause an assertion in unpackFromMemLoc.. This would only trigger in the presence of the F extension making f32 a legal type. Otherwise the f32 would be legalized. This patch fixes that by keeping LocVT=f32 when a float is passed on the stack. It also adds test coverage for this case, and tests that also demonstrate lw/sw/flw/fsw will be selected when most profitable. i.e. there is no unnecessary i32<->f32 conversion in registers. llvm-svn: 343756
* [RISCV] Remove RV64 test lines from umulo-128-legalisation-lowering.llAlex Bradbury2018-10-031-29/+0
| | | | | | | The generated code is incorrect anyway, and this test adds noise to the upcoming set of patches that flesh out RV64 support. llvm-svn: 343675
* [RISCV] Codegen for i8, i16, and i32 atomicrmw with RV32AAlex Bradbury2018-09-191-0/+4282
| | | | | | | | | | | | | | | | | | | | Introduce a new RISCVExpandPseudoInsts pass to expand atomic pseudo-instructions after register allocation. This is necessary in order to ensure that register spills aren't introduced between LL and SC, thus breaking the forward progress guarantee for the operation. AArch64 does something similar for CmpXchg (though only at O0), and Mips is moving towards this approach (see D31287). See also [this mailing list post](http://lists.llvm.org/pipermail/llvm-dev/2016-May/099490.html) from James Knight, which summarises the issues with lowering to ll/sc in IR or pre-RA. See the [accompanying RFC thread](http://lists.llvm.org/pipermail/llvm-dev/2018-June/123993.html) for an overview of the lowering strategy. Differential Revision: https://reviews.llvm.org/D47882 llvm-svn: 342534
* [RISCV] atomic_store_nn have a different layout to regular storeRoger Ferrer Ibanez2018-08-271-12/+12
| | | | | | | | | | | We cannot directy reuse the patterns of StPat because for some reason the store DAG node and the atomic_store_nn DAG nodes put the ptr and the value in different positions. Currently we attempt to store the address to an address formed by the value. Differential Revision: https://reviews.llvm.org/D51217 llvm-svn: 340722
* [SelectionDAG] Improve the legalisation lowering of UMULO.Eli Friedman2018-08-161-0/+175
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There is no way in the universe, that doing a full-width division in software will be faster than doing overflowing multiplication in software in the first place, especially given that this same full-width multiplication needs to be done anyway. This patch replaces the previous implementation with a direct lowering into an overflowing multiplication algorithm based on half-width operations. Correctness of the algorithm was verified by exhaustively checking the output of this algorithm for overflowing multiplication of 16 bit integers against an obviously correct widening multiplication. Baring any oversights introduced by porting the algorithm to DAG, confidence in correctness of this algorithm is extremely high. Following table shows the change in both t = runtime and s = space. The change is expressed as a multiplier of original, so anything under 1 is “better” and anything above 1 is worse. +-------+-----------+-----------+-------------+-------------+ | Arch | u64*u64 t | u64*u64 s | u128*u128 t | u128*u128 s | +-------+-----------+-----------+-------------+-------------+ | X64 | - | - | ~0.5 | ~0.64 | | i686 | ~0.5 | ~0.6666 | ~0.05 | ~0.9 | | armv7 | - | ~0.75 | - | ~1.4 | +-------+-----------+-----------+-------------+-------------+ Performance numbers have been collected by running overflowing multiplication in a loop under `perf` on two x86_64 (one Intel Haswell, other AMD Ryzen) based machines. Size numbers have been collected by looking at the size of function containing an overflowing multiply in a loop. All in all, it can be seen that both performance and size has improved except in the case of armv7 where code size has regressed for 128-bit multiply. u128*u128 overflowing multiply on 32-bit platforms seem to benefit from this change a lot, taking only 5% of the time compared to original algorithm to calculate the same thing. The final benefit of this change is that LLVM is now capable of lowering the overflowing unsigned multiply for integers of any bit-width as long as the target is capable of lowering regular multiplication for the same bit-width. Previously, 128-bit overflowing multiply was the widest possible. Patch by Simonas Kazlauskas! Differential Revision: https://reviews.llvm.org/D50310 llvm-svn: 339922
* [RISCV][MC] Don't fold symbol differences if ↵Alex Bradbury2018-08-161-0/+46
| | | | | | | | | | | | | | | | | | | | | | requiresDiffExpressionRelocations is true When emitting the difference between two symbols, the standard behavior is that the difference will be resolved to an absolute value if both of the symbols are offsets from the same data fragment. This is undesirable on architectures such as RISC-V where relaxation in the linker may cause the computed difference to become invalid. This caused an issue when compiling to object code, where the size of a function in the debug information was already calculated even though it could change as a consequence of relaxation in the subsequent linking stage. This patch inhibits the resolution of symbol differences to absolute values where the target's AsmBackend has declared that it does not want these to be folded. Differential Revision: https://reviews.llvm.org/D45773 Patch by Edward Jones. llvm-svn: 339864
* [RISCV] Fixed test case failure due to r338047Ana Pazos2018-07-311-1/+1
| | | | llvm-svn: 338341
* [RISCV] Add support for _interrupt attributeAna Pazos2018-07-265-0/+1317
| | | | | | | | | | | | | | | | | | | | | - Save/restore only registers that are used. This includes Callee saved registers and Caller saved registers (arguments and temporaries) for integer and FP registers. - If there is a call in the interrupt handler, save/restore all Caller saved registers (arguments and temporaries) and all FP registers. - Emit special return instructions depending on "interrupt" attribute type. Based on initial patch by Zhaoshi Zheng. Reviewers: asb Reviewed By: asb Subscribers: rkruppe, the_o, MartinMosbeck, brucehoult, rbar, johnrusso, simoncook, sabuasal, niosHD, kito-cheng, shiva0217, zzheng, edward-jones, mgrang, rogfer01, llvm-commits Differential Revision: https://reviews.llvm.org/D48411 llvm-svn: 338047
* [RISCV] Add machine function pass to merge base + offsetSameer AbuAsal2018-06-271-37/+38
| | | | | | | | | | | | | | | | | | | | | | | | Summary: In r333455 we added a peephole to fix the corner cases that result from separating base + offset lowering of global address.The peephole didn't handle some of the cases because it only has a basic block view instead of a function level view. This patch replaces that logic with a machine function pass. In addition to handling the original cases it handles uses of the global address across blocks in function and folding an offset from LW\SW instruction. This pass won't run for OptNone compilation, so there will be a negative impact overall vs the old approach at O0. Reviewers: asb, apazos, mgrang Reviewed By: asb Subscribers: MartinMosbeck, brucehoult, the_o, rogfer01, mgorny, rbar, johnrusso, simoncook, niosHD, kito-cheng, shiva0217, zzheng, llvm-commits, edward-jones Differential Revision: https://reviews.llvm.org/D47857 llvm-svn: 335786
* [RISC-V] Fix a test case to not include label names as those aren'tChandler Carruth2018-06-211-2/+2
| | | | | | | stable in non-asserts builds. This fixes a test failure in release config. llvm-svn: 335202
* [RISCV] Add tests for overflow intrinsicsRoger Ferrer Ibanez2018-06-191-0/+84
| | | | | | | This is using the existing codegen so we can see the change once we custom lower ISD::{U,S}{ADD,SUB}O nodes. llvm-svn: 335023
* [RISCV] Add codegen support for atomic load/stores with RV32AAlex Bradbury2018-06-131-0/+217
| | | | | | | | | | | | | | | Fences are inserted according to table A.6 in the current draft of version 2.3 of the RISC-V Instruction Set Manual, which incorporates the memory model changes and definitions contributed by the RISC-V Memory Consistency Model task group. Instruction selection failures will now occur for 8/16/32-bit atomicrmw and cmpxchg operations when targeting RV32IA until lowering for these operations is added in a follow-on patch. Differential Revision: https://reviews.llvm.org/D47589 llvm-svn: 334591
* [RISCV] Codegen support for atomic operations on RV32IAlex Bradbury2018-06-134-0/+7345
| | | | | | | | | | | | | | | | | This patch adds lowering for atomic fences and relies on AtomicExpandPass to lower atomic loads/stores, atomic rmw, and cmpxchg to __atomic_* libcalls. test/CodeGen/RISCV/atomic-* are modelled on the exhaustive test/CodeGen/PPC/atomics-regression.ll, and will prove more useful once RV32A codegen support is introduced. Fence mappings are taken from table A.6 in the current draft of version 2.3 of the RISC-V Instruction Set Manual, which incorporates the memory model changes and definitions contributed by the RISC-V Memory Consistency Model task group. Differential Revision: https://reviews.llvm.org/D47587 llvm-svn: 334590
* [RISCV] Add peepholes for Global Address lowering patternsSameer AbuAsal2018-05-291-16/+73
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: Base and offset are always separated when a GlobalAddress node is lowered (rL332641) as an optimization to reduce instruction count. However, this optimization is not profitable if the Global Address ends up being used in only instruction. This patch adds peephole optimizations that merge an offset of an address calculation into the LUI %%hi and ADD %lo of the lowering sequence. The peephole handles three patterns: 1) ADDI (ADDI (LUI %hi(global)) %lo(global)), offset ---> ADDI (LUI %hi(global + offset)) %lo(global + offset). This generates: lui a0, hi (global + offset) add a0, a0, lo (global + offset) Instead of lui a0, hi (global) addi a0, hi (global) addi a0, offset This pattern is for cases when the offset is small enough to fit in the immediate filed of ADDI (less than 12 bits). 2) ADD ((ADDI (LUI %hi(global)) %lo(global)), (LUI hi_offset)) ---> offset = hi_offset << 12 ADDI (LUI %hi(global + offset)) %lo(global + offset) Which generates the ASM: lui a0, hi(global + offset) addi a0, lo(global + offset) Instead of: lui a0, hi(global) addi a0, lo(global) lui a1, (offset) add a0, a0, a1 This pattern is for cases when the offset doesn't fit in an immediate field of ADDI but the lower 12 bits are all zeros. 3) ADD ((ADDI (LUI %hi(global)) %lo(global)), (ADDI lo_offset, (LUI hi_offset))) ---> offset = global + offhi20<<12 + offlo12 ADDI (LUI %hi(global + offset)) %lo(global + offset) Which generates the ASM: lui a1, %hi(global + offset) addi a1, %lo(global + offset) Instead of: lui a0, hi(global) addi a0, lo(global) lui a1, (offhi20) addi a1, (offlo12) add a0, a0, a1 This pattern is for cases when the offset doesn't fit in an immediate field of ADDI and both the lower 1 bits and high 20 bits are non zero. Reviewers: asb Reviewed By: asb Subscribers: rbar, johnrusso, simoncook, jordy.potman.lists, apazos, niosHD, kito-cheng, shiva0217, zzheng, edward-jones, mgrang llvm-svn: 333455
* [RISCV] Lower the tail pseudoinstructionMandeep Singh Grang2018-05-233-0/+224
| | | | | | | This patch lowers the tail pseudoinstruction. This has been modeled after ARM's tail call opt. llvm-svn: 333137
* [RISCV] Set CostPerUse for registersSameer AbuAsal2018-05-234-57/+57
| | | | | | | | | | | | | | | | | | | Summary: Set CostPerUse higher for registers that are not used in the compressed instruction set. This will influence the greedy register allocator to reduce the use of registers that can't be encoded in 16 bit instructions. This affects register allocation even when compressed instruction isn't targeted, we see no major negative codegen impact. Reviewers: asb Reviewed By: asb Subscribers: rbar, johnrusso, simoncook, jordy.potman.lists, apazos, niosHD, kito-cheng, shiva0217, zzheng, edward-jones, mgrang Differential Revision: https://reviews.llvm.org/D47039 llvm-svn: 333132
* [RISCV] Separate base from offset in lowerGlobalAddressSameer AbuAsal2018-05-178-80/+181
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: When lowering global address, lower the base as a TargetGlobal first then create an SDNode for the offset separately and chain it to the address calculation This optimization will create a DAG where the base address of a global access will be reused between different access. The offset can later be folded into the immediate part of the memory access instruction. With this optimization we generate: lui a0, %hi(s) addi a0, a0, %lo(s) ; shared base address. addi a1, zero, 20 ; 2 instructions per access. sw a1, 44(a0) addi a1, zero, 10 sw a1, 8(a0) addi a1, zero, 30 sw a1, 80(a0) Instead of: lui a0, %hi(s+44) ; 3 instructions per access. addi a1, zero, 20 sw a1, %lo(s+44)(a0) lui a0, %hi(s+8) addi a1, zero, 10 sw a1, %lo(s+8)(a0) lui a0, %hi(s+80) addi a1, zero, 30 sw a1, %lo(s+80)(a0) Which will save one instruction per access. Reviewers: asb, apazos Reviewed By: asb Subscribers: rbar, johnrusso, simoncook, jordy.potman.lists, niosHD, kito-cheng, shiva0217, zzheng, edward-jones, mgrang, apazos, asb, llvm-commits Differential Revision: https://reviews.llvm.org/D46989 llvm-svn: 332641
* [RISCV] Set isReMaterializable on ADDI and LUI instructionsAlex Bradbury2018-05-171-38/+29
| | | | | | | | | | | | | | | | | | | | | | | | | | The isReMaterlizable flag is somewhat confusing, unlike most other instruction flags it is currently interpreted as a hint (mightBeRematerializable would be a better name). While LUI is always rematerialisable, for an instruction like ADDI it depends on its operands. TargetInstrInfo::isTriviallyReMaterializable will call TargetInstrInfo::isReallyTriviallyReMaterializable, which in turn calls TargetInstrInfo::isReallyTriviallyReMaterializableGeneric. We rely on the logic in the latter to pick out instances of ADDI that really are rematerializable. The isReMaterializable flag does make a difference on a variety of test programs. The recently committed remat.ll test case demonstrates how stack usage is reduce and a unnecessary lw/sw can be removed. Stack usage in the Proc0 function in dhrystone reduces from 192 bytes to 112 bytes. For the sake of completeness, this patch also implements RISCVRegisterInfo::isConstantPhysReg. Although this is called from a number of places, it doesn't seem to result in different codegen for any programs I've thrown at it. However, it is called in the rematerialisation codepath and it seems sensible to implement something correct here. Differential Revision: https://reviews.llvm.org/D46182 llvm-svn: 332617
* [RISCV] Support .option rvc and norvc assembler directivesAlex Bradbury2018-05-112-0/+30
| | | | | | | | | | These directives allow the 'C' (compressed) extension to be enabled/disabled within a single file. Differential Revision: https://reviews.llvm.org/D45864 Patch by Kito Cheng llvm-svn: 332107
* [RISCV] Add remat.ll test caseAlex Bradbury2018-04-271-0/+209
| | | | | | | This test case demonstrates suboptimal codegen due to the fact that simple constants aren't recognised as rematerialisable. llvm-svn: 331028
* [RISCV] Implement isZextFreeAlex Bradbury2018-04-261-10/+7
| | | | | | | This returns true for 8-bit and 16-bit loads, allowing LBU/LHU to be selected and avoiding unnecessary masks. llvm-svn: 330943
* [RISCV] Add test case showing suboptimal codegen when loading unsigned ↵Alex Bradbury2018-04-261-0/+79
| | | | | | | | | char/short Implementing isZextFree will allow lbu or lhu to be selected rather than lb+mask and lh+mask. llvm-svn: 330942
* [RISCV] Implement isLegalAddImmediateAlex Bradbury2018-04-261-12/+11
| | | | | | | This causes a trivial improvement in the recently added lsr-legaladdimm.ll test case. llvm-svn: 330937
* [RISCV] Add test/CodeGen/RISCV/lsr-legaladdimm.llAlex Bradbury2018-04-261-0/+49
| | | | | | | Add a test case which will show a codegen difference upon the implementation of a target-specific isLegalAddImmediate. llvm-svn: 330936
* [RISCV] Expand function call to "call" pseudoinstructionShiva Chen2018-04-2523-555/+231
| | | | | | | | | | | | | | | | To do this: 1. Change GlobalAddress SDNode to TargetGlobalAddress to avoid legalizer split the symbol. 2. Change ExternalSymbol SDNode to TargetExternalSymbol to avoid legalizer split the symbol. 3. Let PseudoCALL match direct call with target operand TargetGlobalAddress and TargetExternalSymbol. Differential Revision: https://reviews.llvm.org/D44885 llvm-svn: 330827
* [RISCV] Add test changes missed from rL330293Alex Bradbury2018-04-181-4/+0
| | | | llvm-svn: 330294
* [RISCV] Introduce pattern for materialising immediates with 0 for lower 12 bitsAlex Bradbury2018-04-185-52/+29
| | | | | | | These immediates can be materialised with just an lui, rather than an lui+addi pair. llvm-svn: 330293
* [RISCV] Add imm-cse.ll test caseAlex Bradbury2018-04-181-0/+39
| | | | | | | | | This test case demonstrates that common subexpression elimination takes place between code sequences for materialising constants. In particular, it demonstrates that redundant lui aren't generated. This would capture a regression if applying a patch such as D41949. llvm-svn: 330291
* [RISCV] Expand codegen -> compression sanity checks and move to a single fileAlex Bradbury2018-04-184-85/+169
| | | | | | | | | | The objdump tests interfere with update_llc_test_checks.py and can't be automatically update them. Put the sanitify check for compression on the codegen codepath into a separate file, and expand it to also include tests of integer materialisation. This would catch changes such as those triggered by D41949. llvm-svn: 330288
* Revert "[RISCV] implement li pseudo instruction"Alex Bradbury2018-04-185-104/+127
| | | | | | | | | Reverts rL330224, while issues with the C extension and missed common subexpression elimination opportunities are addressed. Neither of these issues are visible in current RISC-V backend unit tests, which clearly need expanding. llvm-svn: 330281
* [RISCV] Add specific tests for materialising imm32hi20 constantsAlex Bradbury2018-04-181-0/+16
| | | | | | | i.e. constants that can be materialised with a single lui, as the lower 12 bits are zero. llvm-svn: 330274
* [RISCV] implement li pseudo instructionAlex Bradbury2018-04-174-125/+104
| | | | | | | | | | | | | | The implementation follows the MIPS backend and expands the pseudo instruction directly during asm parsing. As the result, only real MC instructions are emitted to the MCStreamer. Additionally, PseudoLI instructions are emitted during codegen. The actual expansion to real instructions is performed during MI to MC lowering and is similar to the expansion performed by the GNU Assembler. Differential Revision: https://reviews.llvm.org/D41949 Patch by Mario Werner. llvm-svn: 330224
* [RISCV] Change function alignment to 4 bytes, and 2 bytes for RVCShiva Chen2018-04-121-0/+13
| | | | | | | | | | | | | | | | | | Summary: According RISC-V ELF psABI specification, base RV32 and RV64 ISAs only allow 32-bit instruction alignment, but instruction allow to be aligned to 16-bit boundaries for C-extension. So we just align to 4 bytes and 2 bytes for C-extension is enough. Reviewers: asb, apazos Differential Revision: https://reviews.llvm.org/D45560 Patch by Kito Cheng. llvm-svn: 329899
* [RISCV] Codegen support for RV32D floating point comparison operationsAlex Bradbury2018-04-124-0/+1327
| | | | | | | | Also add double-prevoius-failure.ll which captures a test case that at one point triggered a compiler crash, while developing calling convention support for f64 on RV32D with soft-float ABI. llvm-svn: 329877
* [RISCV] Codegen support for RV32D floating point conversion operationsAlex Bradbury2018-04-122-0/+106
| | | | | | | This also includes support and a test for truncating stores, which are now possible thanks to the fpround pattern. llvm-svn: 329876
* [RISCV] Add codegen support for RV32D floating point arithmetic operationsAlex Bradbury2018-04-121-0/+256
| | | | llvm-svn: 329874
* [RISCV] Add tests missed in r329871Alex Bradbury2018-04-126-0/+464
| | | | llvm-svn: 329872
OpenPOWER on IntegriCloud