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* [RISCV] Add RISCV-specific TargetTransformInfoSam Elliott2019-06-211-11/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: LLVM Allows Targets to provide information that guides optimisations made to LLVM IR. This is done with callbacks on a TargetTransformInfo object. This patch adds a TargetTransformInfo class for RISC-V. This will allow us to implement RISC-V specific callbacks as they become necessary. This commit also adds the getIntImmCost callbacks, and tests them with a simple constant hoisting test. Our immediate costs are on the conservative side, for the moment, but we prevent hoisting in most circumstances anyway. Previous review was on D63007 Reviewers: asb, luismarques Reviewed By: asb Subscribers: ributzka, MaskRay, llvm-commits, Jim, benna, psnobl, jocewei, PkmX, rkruppe, the_o, brucehoult, MartinMosbeck, rogfer01, edward-jones, zzheng, jrtc27, shiva0217, kito-cheng, niosHD, sabuasal, apazos, simoncook, johnrusso, rbar, hiraditya, mgorny Tags: #llvm Differential Revision: https://reviews.llvm.org/D63433 llvm-svn: 364046
* [RISCV] Add lowering of global TLS addressesLewis Revill2019-06-191-0/+155
| | | | | | | | | | | | | This patch adds lowering for global TLS addresses for the TLS models of InitialExec, GlobalDynamic, LocalExec and LocalDynamic. LocalExec support required using a 4-operand add instruction, which uses the fourth operand to express a relocation on the symbol. The necessary fixup is emitted when the instruction is emitted. Differential Revision: https://reviews.llvm.org/D55305 llvm-svn: 363771
* [RISCV] Fix test after r363757Alex Bradbury2019-06-191-2/+2
| | | | | | | r363757 renamed ExpandISelPseudo to FinalizeISel, so the RUN line in select-optimize-multiple.mir needed updating to refer to finalize-isel. llvm-svn: 363762
* [RISCV] Prevent re-ordering some adds after shiftsSam Elliott2019-06-181-0/+74
| | | | | | | | | | | | | | | | | | | | | | | | | Summary: DAGCombine will normally turn a `(shl (add x, c1), c2)` into `(add (shl x, c2), c1 << c2)`, where `c1` and `c2` are constants. This can be prevented by a callback in TargetLowering. On RISC-V, materialising the constant `c1 << c2` can be more expensive than materialising `c1`, because materialising the former may take more instructions, and may use a register, where materialising the latter would not. This patch implements the hook in RISCVTargetLowering to prevent this transform, in the cases where: - `c1` fits into the immediate field in an `addi` instruction. - `c1` takes fewer instructions to materialise than `c1 << c2`. In future, DAGCombine could do the check to see whether `c1` fits into an add immediate, which might simplify more targets hooks than just RISC-V. Reviewers: asb, luismarques, efriedma Reviewed By: asb Subscribers: xbolva00, lebedev.ri, craig.topper, lewis-revill, Jim, hiraditya, rbar, johnrusso, simoncook, apazos, sabuasal, niosHD, kito-cheng, shiva0217, jrtc27, zzheng, edward-jones, rogfer01, MartinMosbeck, brucehoult, the_o, rkruppe, PkmX, jocewei, psnobl, benna, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D62857 llvm-svn: 363736
* [RISCV] Lower calls through PLTLewis Revill2019-06-181-0/+124
| | | | | | | | | | This patch adds support for generating calls through the procedure linkage table where required for a given ExternalSymbol or GlobalAddress callee. Differential Revision: https://reviews.llvm.org/D55304 llvm-svn: 363686
* [DAGCombiner] [CodeGenPrepare] More comprehensive GEP splittingLuis Marques2019-06-171-0/+126
| | | | | | | | | | | | | | | Some GEPs were not being split, presumably because that split would just be undone by the DAGCombiner. Not performing those splits can prevent important optimizations, such as preventing the element indices / member offsets from being (partially) folded into load/store instruction immediates. This patch: - Makes the splits also occur in the cases where the base address and the GEP are in the same BB. - Ensures that the DAGCombiner doesn't reassociate them back again. Differential Revision: https://reviews.llvm.org/D60294 llvm-svn: 363544
* [RISCV] Regenerate remat.ll and atomic-rmw.ll after D43256Fangrui Song2019-06-152-2386/+2589
| | | | llvm-svn: 363487
* [RISCV] Fix inline-asm.ll test by adding nounwind attributeAlex Bradbury2019-06-121-3/+3
| | | | | | This test failed since CFI directive support was added in r361320. llvm-svn: 363123
* [RISCV] Add CFI directives for RISCV prologue/epilog.Hsiangkai Wang2019-06-121-0/+66
| | | | | | | | | In order to generate correct debug frame information, it needs to generate CFI information in prologue and epilog. Differential Revision: https://reviews.llvm.org/D61773 llvm-svn: 363120
* [RISCV] Add lowering of addressing sequences for PICLewis Revill2019-06-111-0/+85
| | | | | | | | | | This patch allows lowering of PIC addresses by using PC-relative addressing for DSO-local symbols and accessing the address through the global offset table for non-DSO-local symbols. Differential Revision: https://reviews.llvm.org/D55303 llvm-svn: 363058
* [RISCV][NFC] Add missing test file for D54093Lewis Revill2019-06-111-0/+24
| | | | llvm-svn: 363057
* [RISCV] Lower inline asm constraints I, J & K for RISC-VLewis Revill2019-06-111-0/+68
| | | | | | | | | | | | | This validates and lowers arguments to inline asm nodes which have the constraints I, J & K, with the following semantics (equivalent to GCC): I: Any 12-bit signed immediate. J: Immediate integer zero only. K: Any 5-bit unsigned immediate. Differential Revision: https://reviews.llvm.org/D54093 llvm-svn: 363054
* [RISCV] Support Bit-Preserving FP in F/D ExtensionsSam Elliott2019-06-071-0/+390
| | | | | | | | | | | | | | | | | | | | | | | | Summary: This allows some integer bitwise operations to instead be performed by hardware fp instructions. This is correct because the RISC-V spec requires the F and D extensions to use the IEEE-754 standard representation, and fp register loads and stores to be bit-preserving. This is tested against the soft-float ABI, but with hardware float extensions enabled, so that the tests also ensure the optimisation also fires in this case. Reviewers: asb, luismarques Reviewed By: asb Subscribers: hiraditya, rbar, johnrusso, simoncook, apazos, sabuasal, niosHD, kito-cheng, shiva0217, jrtc27, zzheng, edward-jones, rogfer01, MartinMosbeck, brucehoult, the_o, rkruppe, PkmX, jocewei, psnobl, benna, Jim, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D62900 llvm-svn: 362790
* [RISCV][NFC] Add nounwind attribute to functions missing it in ↵Alex Bradbury2019-05-2318-84/+83
| | | | | | | | test/CodeGen/RISCV r360897 was incomplete, must have applied an old/wip patch. This is in preparation for emitting CFI directives. llvm-svn: 361493
* [TargetLowering] Extend bool args to inline-asm according to getBooleanTypeKees Cook2019-05-221-0/+14
| | | | | | | | | | | | | | | | | Summary: This extends Krzysztof Parzyszek's X86-specific solution (https://reviews.llvm.org/D60208) to the generic code pointed out by James Y Knight. Reviewers: kparzysz, craig.topper, nickdesaulniers Subscribers: efriedma, sdardis, nemanjai, javed.absar, eraman, fedor.sergeev, asb, rbar, johnrusso, simoncook, apazos, sabuasal, niosHD, jrtc27, zzheng, edward-jones, atanasyan, rogfer01, MartinMosbeck, brucehoult, the_o, PkmX, jocewei, jsji, llvm-commits, srhines, void, nickdesaulniers, jyknight Tags: #llvm Differential Revision: https://reviews.llvm.org/D60224 llvm-svn: 361404
* [RISCV][NFC] Add nounwind attribute to functions missing it in ↵Alex Bradbury2019-05-169-119/+119
| | | | | | | | test/CodeGen/RISCV This is in preparation for emitting CFI directives. llvm-svn: 360897
* [IR] Disallow llvm.global_ctors and llvm.global_dtors of the 2-field form in ↵Fangrui Song2019-05-151-1/+1
| | | | | | | | | | | | | | | | | | | | textual format The 3-field form was introduced by D3499 in 2014 and the legacy 2-field form was planned to be removed in LLVM 4.0 For the textual format, this patch migrates the existing 2-field form to use the 3-field form and deletes the compatibility code. test/Verifier/global-ctors-2.ll checks we have a friendly error message. For bitcode, lib/IR/AutoUpgrade UpgradeGlobalVariables will upgrade the 2-field form (add i8* null as the third field). Reviewed By: rnk, dexonsmith Differential Revision: https://reviews.llvm.org/D61547 llvm-svn: 360742
* [SelectionDAG] Expand ADD/SUBCARRYLeonard Chan2019-05-091-0/+44
| | | | | | | | This patch allows for expansion of ADDCARRY and SUBCARRY when the target does not support it. Differential Revision: https://reviews.llvm.org/D61411 llvm-svn: 360303
* [RISCV] Custom lower SHL_PARTS, SRA_PARTS, SRL_PARTSLuis Marques2019-04-162-15/+299
| | | | | | | | | When not optimizing for minimum size (-Oz) we custom lower wide shifts (SHL_PARTS, SRA_PARTS, SRL_PARTS) instead of expanding to a libcall. Differential Revision: https://reviews.llvm.org/D59477 llvm-svn: 358498
* [RISCV] Put data smaller than eight bytes to small data sectionShiva Chen2019-04-114-0/+60
| | | | | | | | | | | Because of gp = sdata_start_address + 0x800, gp with signed twelve-bit offset could covert most of the small data section. Linker relaxation could transfer the multiple data accessing instructions to a gp base with signed twelve-bit offset instruction. Differential Revision: https://reviews.llvm.org/D57493 llvm-svn: 358150
* [RISCV] Implement adding a displacement to a BlockAddressRoger Ferrer Ibanez2019-04-051-5/+79
| | | | | | | | | | | | Recent change rL357393 uses MachineInstrBuilder::addDisp to add a based on a BlockAddress but this case was not implemented. This patch adds the missing case and a test for RISC-V that exercises the new case. Differential Revision: https://reviews.llvm.org/D60136 llvm-svn: 357752
* [RISCV] Generate address sequences suitable for mcmodel=mediumAlex Bradbury2019-04-011-0/+80
| | | | | | | | | | | | | | | | | This patch adds an implementation of a PC-relative addressing sequence to be used when -mcmodel=medium is specified. With absolute addressing, a 'medium' codemodel may cause addresses to be out of range. This is because while 'medium' implies a 2 GiB addressing range, this 2 GiB can be at any offset as opposed to 'small', which implies the first 2 GiB only. Note that LLVM/Clang currently specifies code models differently to GCC, where small and medium imply the same functionality as GCC's medlow and medany respectively. Differential Revision: https://reviews.llvm.org/D54143 Patch by Lewis Revill. llvm-svn: 357393
* [RISCV] Add seto pattern expansionLuis Marques2019-04-016-48/+0
| | | | | | | | | Adds a `seto` pattern expansion. Without it the lowerings of `fcmp one` and `fcmp ord` would be inefficient due to an unoptimized double negation. Differential Revision: https://reviews.llvm.org/D59699 llvm-svn: 357378
* [RISCV] Add codegen support for ilp32f, ilp32d, lp64f, and lp64d ("hard ↵Alex Bradbury2019-03-3011-22/+741
| | | | | | | | | | | | | | | | | | | | float") ABIs This patch adds support for the RISC-V hard float ABIs, building on top of rL355771, which added basic target-abi parsing and MC layer support. It also builds on some re-organisations and expansion of the upstream ABI and calling convention tests which were recently committed directly upstream. A number of aspects of the RISC-V float hard float ABIs require frontend support (e.g. flattening of structs and passing int+fp for fp+fp structs in a pair of registers), and will be addressed in a Clang patch. As can be seen from the tests, it would be worthwhile extending RISCVMergeBaseOffsets to handle constant pool as well as global accesses. Differential Revision: https://reviews.llvm.org/D59357 llvm-svn: 357352
* [RISCV] Add RV64 CHECK lines to test/CodeGen/RISCV/vararg.ll and prepare for ↵Alex Bradbury2019-03-301-644/+1555
| | | | | | | | | | | | hard float tests vararg.ll previously missed RV64 tests. This patch also prepares for using vararg.ll to test handling of varargs for the ilp32f/ilp32d/lp64f/lp64d hard float ABIs. In these ABIs, varargs are passed as in either the ilp32 or lp64 ABI. Due to some slight codegen differences, different check lines are needed for when RV32D is enabled. llvm-svn: 357350
* [RISCV] Add DAGCombine for (SplitF64 (ConstantFP x))Alex Bradbury2019-03-303-47/+29
| | | | | | | | | | | | The SplitF64 node is used on RV32D to convert an f64 directly to a pair of i32 (necessary as bitcasting to i64 isn't legal). When performed on a ConstantFP, this will result in a FP load from the constant pool followed by a store to the stack and two integer loads from the stack (necessary as there is no way to directly move between f64 FPRs and i32 GPRs on RV32D). It's always cheaper to just materialise integers for the lo and hi parts of the FP constant, so do that instead. llvm-svn: 357341
* [RISCV][NFC] Remove floating point operations from test/CodeGen/RISCV/vararg.llAlex Bradbury2019-03-301-65/+65
| | | | | | | | This minimises differences in output when compiling with hardware floating point support, which will be done in a future patch (to demonstrate the same vararg calling convention is used). llvm-svn: 357339
* [RISCV] Update setcc-logic.ll codegen testLuis Marques2019-03-261-12/+8
| | | | | | This should have been updated as part of D59753. llvm-svn: 357002
* [RISCV] Improve codegen for icmp {ne,eq} with a constantLuis Marques2019-03-261-0/+22
| | | | | | | | | Adds two patterns to improve the codegen of GPR value comparisons with small constants. Instead of first loading the constant into another register and then doing an XOR of those registers, these patterns directly use the constant as an XORI immediate. llvm-svn: 356990
* [RISCV] Add basic RV32E definitions and MC layer supportAlex Bradbury2019-03-222-0/+11
| | | | | | | | | | | | | | | | | | | | | The RISC-V ISA defines RV32E as an alternative "base" instruction set encoding, that differs from RV32I by having only 16 rather than 32 registers. This patch adds basic definitions for RV32E as well as MC layer support (assembling, disassembling) and tests. The only supported ABI on RV32E is ILP32E. Add a new RISCVFeatures::validate() helper to RISCVUtils which can be called from codegen or MC layer libraries to validate the combination of TargetTriple and FeatureBitSet. Other targets have similar checks (e.g. erroring if SPE is enabled on PPC64 or oddspreg + o32 ABI on Mips), but they either duplicate the checks (Mips), or fail to check for both codegen and MC codepaths (PPC). Codegen for the ILP32E ABI support and RV32E codegen are left for a future patch/patches. Differential Revision: https://reviews.llvm.org/D59470 llvm-svn: 356744
* [RISCV] Optimize emission of SELECT sequencesAlex Bradbury2019-03-223-400/+714
| | | | | | | | | | | | | | | | | | | This patch optimizes the emission of a sequence of SELECTs with the same condition, avoiding the insertion of unnecessary control flow. Such a sequence often occurs when a SELECT of values wider than XLEN is legalized into two SELECTs with legal types. We have identified several use cases where the SELECTs could be interleaved with other instructions. Therefore, we extend the sequence to include non-SELECT instructions if we are able to detect that the non-SELECT instructions do not impact the optimization. This patch supersedes https://reviews.llvm.org/D59096, which attempted to address this issue by introducing a new SelectionDAG node. Hat tip to Eli Friedman for his feedback on how to best handle this issue. Differential Revision: https://reviews.llvm.org/D59355 Patch by Luís Marques. llvm-svn: 356741
* [RISCV] Allow conversion of CC logic to bitwise logicAlex Bradbury2019-03-221-0/+130
| | | | | | | | | | | | | Indicates in the TargetLowering interface that conversions from CC logic to bitwise logic are allowed. Adds tests that show the benefit when optimization opportunities are detected. Also adds tests that show that when the optimization is not applied correct code is generated (but opportunities for other optimizations remain). Differential Revision: https://reviews.llvm.org/D59596 Patch by Luís Marques. llvm-svn: 356740
* [RISCV] Extend test/CodeGen/RISCV/callee-saved-* to test getCalleePreservedRegsAlex Bradbury2019-03-143-10/+183
| | | | | | | Add a caller which exhausts regs then calls another function. This allows getCalleePreservedRegs to be tested. llvm-svn: 356122
* [RISCV] Regenerate test/CodeGen/RISCV/legalize-fneg.ll after rL356068Alex Bradbury2019-03-131-22/+4
| | | | | | | | | rL356068 caused some minor re-orderings. Regenerate legalize-fneg.ll to reflect this, and remove the NOLIB check lines (they're redundant given that the RV32I and RV64I check lines generated by update_llc_test_checks.py already demonstrate there is no libcall). llvm-svn: 356074
* [RISCV] Only mark fp as reserved if the function has a dedicated frame pointerAlex Bradbury2019-03-1319-2712/+2714
| | | | | | | | This follows similar logic in the ARM and Mips backends, and allows the free use of s0 in functions without a dedicated frame pointer. The changes in callee-saved-gprs.ll most clearly show the effect of this patch. llvm-svn: 356063
* [RISCV] Add tests for callee-saved GPRs, FPR32s, and FPR64sAlex Bradbury2019-03-133-0/+259
| | | | | | | | Note that s0 need not be marked reserved if the frame pointer isn't used. For the ILP32 and LP64 soft float ABIS that are currently support, all FPRs are always considered temporaries. llvm-svn: 356061
* [RISCV] Regenerate umulo-128-legalisation-lowering.llAlex Bradbury2019-03-131-99/+89
| | | | | | Upstream changes have improved codegen, reducing stack usage. Regenerate the test. llvm-svn: 356044
* [RISCV] Add test cases for the lp64 ABIAlex Bradbury2019-03-123-0/+792
| | | | | | | | These are closely modeled on similar tests for the ilp32 ABI. Like those tests, we group together tests that should be common cross lp64, lp64+lp64f, and lp64+lp64f+lp64d ABIs. llvm-svn: 355899
* [RISCV] Do a sign-extension in a compare-and-swap of 32 bit in RV64AAlex Bradbury2019-03-111-0/+29
| | | | | | | | | | | | | | | | AtomicCmpSwapWithSuccess is legalised into an AtomicCmpSwap plus a comparison. This requires an extension of the value which, by default, is a zero-extension. When we later lower AtomicCmpSwap into a PseudoCmpXchg32 and then expanded in RISCVExpandPseudoInsts.cpp, the lr.w instruction does a sign-extension. This mismatch of extensions causes the comparison to fail when the compared value is negative. This change overrides TargetLowering::getExtendForAtomicOps for RISC-V so it does a sign-extension instead. Differential Revision: https://reviews.llvm.org/D58829 Patch by Ferran Pallarès Roca. llvm-svn: 355869
* [RISCV] Support -target-abi at the MC layer and for codegenAlex Bradbury2019-03-092-0/+98
| | | | | | | | | | | | | | | | This patch adds proper handling of -target-abi, as accepted by llvm-mc and llc. Lowering (codegen) for the hard-float ABIs will follow in a subsequent patch. However, this patch does add MC layer support for the hard float and RVE ABIs (emission of the appropriate ELF flags https://github.com/riscv/riscv-elf-psabi-doc/blob/master/riscv-elf.md#-file-header). ABI parsing must be shared between codegen and the MC layer, so we add computeTargetABI to RISCVUtils. A warning will be printed if an invalid or unrecognized ABI is given. Differential Revision: https://reviews.llvm.org/D59023 llvm-svn: 355771
* [RISCV] Re-organise calling convention testsAlex Bradbury2019-02-193-213/+633
| | | | | | | | Re-organise calling convention tests to prepare for ilp32f and ilp32d hard float ABI tests. It's also clear that we need to introduce similar tests for lp64. llvm-svn: 354323
* [RISCV][NFC] Add RV64I CHECK lines to inline-asm.ll testAlex Bradbury2019-02-141-0/+31
| | | | llvm-svn: 354028
* [LegalizeTypes] Expand FNEG to bitwise op for IEEE FP typesAna Pazos2019-02-111-0/+105
| | | | | | | | | | | | | | | | | Summary: Except for custom floating point types x86_fp80 and ppc_fp128, expand Y = FNEG(X) to Y = X ^ sign mask to avoid library call. Using bitwise operation can improve code size and performance. Reviewers: efriedma Reviewed By: efriedma Subscribers: efriedma, kpn, arsenm, eli.friedman, javed.absar, rbar, johnrusso, simoncook, sabuasal, niosHD, zzheng, edward-jones, rogfer01, MartinMosbeck, brucehoult, the_o, PkmX, jocewei, asb, llvm-commits Differential Revision: https://reviews.llvm.org/D57875 llvm-svn: 353757
* [RISCV] Implement RV64D codegenAlex Bradbury2019-02-0111-0/+1483
| | | | | | | | | | | | This patch: * Adds necessary RV64D codegen patterns * Modifies CC_RISCV so it will properly handle f64 types (with soft float ABI) Note that in general there is no reason to try to select fcvt.w[u].d rather than fcvt.l[u].d for i32 conversions because fptosi/fptoui produce poison if the input won't fit into the target type. Differential Revision: https://reviews.llvm.org/D53237 llvm-svn: 352833
* [SelectionDAG] Support promotion of the FPOWI integer operandAlex Bradbury2019-02-011-0/+218
| | | | | | | | | | | | | | For targets where i32 is not a legal type (e.g. 64-bit RISC-V), LegalizeIntegerTypes must promote the integer operand of ISD::FPOWI. As this is a signed value, this should be sign-extended. This patch enables all tests in test/CodeGen/RISCVfloat-intrinsics.ll for RV64, as prior to this patch that file couldn't be compiled for RV64 due to an assertion when performing codegen for fpowi. Differential Revision: https://reviews.llvm.org/D54574 llvm-svn: 352832
* [RISCV] Add RV64F codegen supportAlex Bradbury2019-01-3110-0/+1336
| | | | | | | | | | | | | This requires a little extra work due tothe fact i32 is not a legal type. When call lowering happens post-legalisation (e.g. when an intrinsic was inserted during legalisation). A bitcast from f32 to i32 can't be introduced. This is similar to the challenges with RV32D. To handle this, we introduce target-specific DAG nodes that perform bitcast+anyext for f32->i64 and trunc+bitcast for i64->f32. Differential Revision: https://reviews.llvm.org/D53235 llvm-svn: 352807
* [RISCV] Add target DAG combine for bitcast fabs/fneg on RV32FDAlex Bradbury2019-01-253-39/+33
| | | | | | | | | | | | | DAGCombiner::visitBITCAST will perform: fold (bitconvert (fneg x)) -> (xor (bitconvert x), signbit) fold (bitconvert (fabs x)) -> (and (bitconvert x), (not signbit)) As shown in double-bitmanip-dagcombines.ll, this can be advantageous. But RV32FD doesn't use bitcast directly (as i64 isn't a legal type), and instead uses RISCVISD::SplitF64. This patch adds an equivalent DAG combine for SplitF64. llvm-svn: 352247
* [RISCV] Add another potential combine to {double,float}-bitmanip-dagcombines.llAlex Bradbury2019-01-252-1/+103
| | | | | | | | (fcopysign a, (fneg b)) will be expanded to bitwise operations by DAGTypeLegalizer::SoftenFloatRes_FCOPYSIGN if the floating point type isn't legal. Arguably it might be worth doing a combine even if it is legal. llvm-svn: 352240
* Reapply: [RISCV] Set isAsCheapAsAMove for ADDI, ORI, XORI, LUIAna Pazos2019-01-259-2139/+1584
| | | | | | This reapplies commit r352010 with RISC-V test fixes. llvm-svn: 352237
* [RISCV][NFC] s/f32/f64 in double-arith.llAlex Bradbury2019-01-251-11/+11
| | | | | | | The intrinsic names erroneously used the .f32 variant. As the return and argument types were still double the intrinsics calls worked properly. llvm-svn: 352211
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