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path: root/llvm/test/CodeGen/RISCV/select-optimize-multiple.ll
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* [RISCV] Switch to the Machine SchedulerLuis Marques2019-09-171-60/+86
| | | | | | | | | Most of the test changes are trivial instruction reorderings and differing register allocations, without any obvious performance impact. Differential Revision: https://reviews.llvm.org/D66973 llvm-svn: 372106
* Revert Patch from PhabricatorLuis Marques2019-09-171-86/+60
| | | | | | This reverts r372092 (git commit e38695a0255c9e7b53639f349f8101bae1ce5c04) llvm-svn: 372104
* Patch from PhabricatorLuis Marques2019-09-171-60/+86
| | | | llvm-svn: 372092
* [RISCV] Custom legalize i32 operations for RV64 to reduce signed extensionsShiva Chen2019-08-061-4/+4
| | | | | | Differential Revision: https://reviews.llvm.org/D65434 llvm-svn: 367960
* [RISCV] Optimize emission of SELECT sequencesAlex Bradbury2019-03-221-0/+323
This patch optimizes the emission of a sequence of SELECTs with the same condition, avoiding the insertion of unnecessary control flow. Such a sequence often occurs when a SELECT of values wider than XLEN is legalized into two SELECTs with legal types. We have identified several use cases where the SELECTs could be interleaved with other instructions. Therefore, we extend the sequence to include non-SELECT instructions if we are able to detect that the non-SELECT instructions do not impact the optimization. This patch supersedes https://reviews.llvm.org/D59096, which attempted to address this issue by introducing a new SelectionDAG node. Hat tip to Eli Friedman for his feedback on how to best handle this issue. Differential Revision: https://reviews.llvm.org/D59355 Patch by Luís Marques. llvm-svn: 356741
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