summaryrefslogtreecommitdiffstats
path: root/llvm/test/CodeGen/RISCV/reserved-reg-errors.ll
Commit message (Collapse)AuthorAgeFilesLines
* [RISCV] Add support for -ffixed-xX flagsSimon Cook2019-10-221-0/+36
This adds support for reserving GPRs such that the compiler will not choose a register for register allocation. The implementation follows the same design as for AArch64; each reserved register becomes a target feature and used for getting the reserved registers for a given MachineFunction. The backend checks that it does not need to write to any reserved register; if it does a relevant error is generated. Differential Revision: https://reviews.llvm.org/D67185
OpenPOWER on IntegriCloud