| Commit message (Collapse) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | [RISCV] Add RV64F codegen support | Alex Bradbury | 2019-01-31 | 1 | -0/+122 |
| | | | | | | | | | | | | | | This requires a little extra work due tothe fact i32 is not a legal type. When call lowering happens post-legalisation (e.g. when an intrinsic was inserted during legalisation). A bitcast from f32 to i32 can't be introduced. This is similar to the challenges with RV32D. To handle this, we introduce target-specific DAG nodes that perform bitcast+anyext for f32->i64 and trunc+bitcast for i64->f32. Differential Revision: https://reviews.llvm.org/D53235 llvm-svn: 352807 | ||||
| * | [RISCV] Add codegen for RV32F arithmetic and conversion operations | Alex Bradbury | 2018-03-20 | 1 | -0/+72 |
| Currently, only a soft floating point ABI is supported. llvm-svn: 327976 | |||||
 |
index : bcm5719-llvm | |
| Project Ortega BCM5719 LLVM | Raptor Computing Systems |
| summaryrefslogtreecommitdiffstats |
|