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path: root/llvm/test/CodeGen/RISCV/double-select-fcmp.ll
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* [RISCV] Switch to the Machine SchedulerLuis Marques2019-09-171-25/+25
| | | | | | | | | Most of the test changes are trivial instruction reorderings and differing register allocations, without any obvious performance impact. Differential Revision: https://reviews.llvm.org/D66973 llvm-svn: 372106
* Revert Patch from PhabricatorLuis Marques2019-09-171-25/+25
| | | | | | This reverts r372092 (git commit e38695a0255c9e7b53639f349f8101bae1ce5c04) llvm-svn: 372104
* Patch from PhabricatorLuis Marques2019-09-171-25/+25
| | | | llvm-svn: 372092
* [RISCV] Add seto pattern expansionLuis Marques2019-04-011-8/+0
| | | | | | | | | Adds a `seto` pattern expansion. Without it the lowerings of `fcmp one` and `fcmp ord` would be inefficient due to an unoptimized double negation. Differential Revision: https://reviews.llvm.org/D59699 llvm-svn: 357378
* [RISCV] Implement RV64D codegenAlex Bradbury2019-02-011-0/+215
| | | | | | | | | | | | This patch: * Adds necessary RV64D codegen patterns * Modifies CC_RISCV so it will properly handle f64 types (with soft float ABI) Note that in general there is no reason to try to select fcvt.w[u].d rather than fcvt.l[u].d for i32 conversions because fptosi/fptoui produce poison if the input won't fit into the target type. Differential Revision: https://reviews.llvm.org/D53237 llvm-svn: 352833
* [RISCV] Regenerate several tests now enableMultipleCopyHints is enabled by ↵Alex Bradbury2018-10-051-1/+1
| | | | | | | | default r343851 caused codegen changes in several tests. This patch regenerates them. llvm-svn: 343873
* [RISCV] Codegen support for RV32D floating point comparison operationsAlex Bradbury2018-04-121-0/+423
Also add double-prevoius-failure.ll which captures a test case that at one point triggered a compiler crash, while developing calling convention support for f64 on RV32D with soft-float ABI. llvm-svn: 329877
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