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path: root/llvm/test/CodeGen/R600/local-memory-two-objects.ll
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* R600/SI: Match i16 immediate offset of LDS instructions.Matt Arsenault2014-03-191-3/+4
| | | | llvm-svn: 204272
* R600/SI: Don't display the GDS bit.Matt Arsenault2014-03-191-4/+4
| | | | | | | | It isn't actually used now, and probably never will be, plus it makes tests less annoying. I also think SC prints GDS instructions as a separate instruction name. llvm-svn: 204270
* R600: Fix scheduling of instructions that use the LDS output queueTom Stellard2013-11-151-3/+5
| | | | | | | | | | | | | | | | | | | | | | | | The LDS output queue is accessed via the OQAP register. The OQAP register cannot be live across clauses, so if value is written to the output queue, it must be retrieved before the end of the clause. With the machine scheduler, we cannot statisfy this constraint, because it lacks proper alias analysis and it will mark some LDS accesses as having a chain dependency on vertex fetches. Since vertex fetches require a new clauses, the dependency may end up spiltting OQAP uses and defs so the end up in different clauses. See the lds-output-queue.ll test for a more detailed explanation. To work around this issue, we now combine the LDS read and the OQAP copy into one instruction and expand it after register allocation. This patch also adds some checks to the EmitClauseMarker pass, so that it doesn't end a clause with a value still in the output queue and removes AR.X and OQAP handling from the scheduler (AR.X uses and defs were already being expanded post-RA, so the scheduler will never see them). Reviewed-by: Vincent Lejeune <vljn at ovi.com> llvm-svn: 194755
* R600/SI: Change formatting of printed registers.Matt Arsenault2013-11-121-4/+4
| | | | | | | | | | | | | | | | | | | | | | | Print the range of registers used with a single letter prefix. This better matches what the shader compiler produces and is overall less obnoxious than concatenating all of the subregister names together. Instead of SGPR0, it will print s0. Instead of SGPR0_SGPR1, it will print s[0:1] and so on. There doesn't appear to be a straightforward way to get the actual register info in the InstPrinter, so this parses the generated name to print with the new syntax. The required test changes are pretty nasty, and register matching regexes are now worse. Since there isn't a way to add to a variable in FileCheck, some of the tests now don't check the exact number of registers used, but I don't think that will be a real problem. llvm-svn: 194443
* R600/SI: Use -verify-machineinstrs for most testsTom Stellard2013-10-101-1/+1
| | | | | | | | | | We can't enable the verifier for tests with SI_IF and SI_ELSE, because these instructions are always followed by a COPY which copies their result to the next basic block. This violates the machine verifier's rule that non-terminators can not folow terminators. Reviewed-by: Vincent Lejeune<vljn at ovi.com> llvm-svn: 192366
* R600/SI: Enable local-memory-two-objects lit testMichel Danzer2013-08-271-12/+17
| | | | | Reviewed-by: Tom Stellard <thomas.stellard@amd.com> llvm-svn: 189334
* Revert "R600: Non vector only instruction can be scheduled on trans unit"Tom Stellard2013-07-311-1/+1
| | | | | | This reverts commit 98ce62780ea7185ba710868bf83c8077e8d7f6d6. llvm-svn: 187526
* R600: Non vector only instruction can be scheduled on trans unitVincent Lejeune2013-07-311-1/+1
| | | | llvm-svn: 187514
* R600/SI: Initial local memory supportMichel Danzer2013-07-101-0/+51
Enough for the radeonsi driver to use it for calculating derivatives. Reviewed-by: Tom Stellard <thomas.stellard@amd.com> llvm-svn: 186012
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