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* [PowerPC] Remove redundant CRSET/CRUNSET in custom lowering of known CR bit ↵Yi-Hong Lyu2019-11-081-2/+5
| | | | | | | | | | | | | | | | | | | | | | spills We lower known CR bit spills (CRSET/CRUNSET) to load and spill the known value but forgot to remove the redundant spills. e.g., This sequence was used to spill a CRUNSET: crclr 4*cr5+lt mfocrf r3,4 rlwinm r3,r3,20,0,0 stw r3,132(r1) Custom lowering of known CR bit spills lower it to: crxor 4*cr5+lt, 4*cr5+lt, 4*cr5+lt li r3,0 stw r3,132(r1) crxor is redundant if there is no use of 4*cr5+lt so we should remove it Differential revision: https://reviews.llvm.org/D67722
* [XCOFF][AIX] Differentiate usage of label symbol and csect symbolJason Liu2019-11-082-10/+10
| | | | | | | | | | | | | | | | | | | | | | | | | Summary: We are using symbols to represent label and csect interchangeably before, and that could be a problem. There are cases we would need to add storage mapping class to the symbol if that symbol is actually the name of a csect, but it's hard for us to figure out whether that symbol is a label or csect. This patch intend to do the following: 1. Construct a QualName (A name include the storage mapping class) MCSymbolXCOFF for every MCSectionXCOFF. 2. Keep a pointer to that QualName inside of MCSectionXCOFF. 3. Use that QualName whenever we need a symbol refers to that MCSectionXCOFF. 4. Adapt the snowball effect from the above changes in XCOFFObjectWriter.cpp. Reviewers: xingxue, DiggerLin, sfertile, daltenty, hubert.reinterpretcast Reviewed By: DiggerLin, daltenty Subscribers: wuzish, nemanjai, mgorny, hiraditya, kbarton, jsji, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D69633
* [PowerPC] Option for enabling absolute jumptables with command lineNemanja Ivanovic2019-11-071-0/+100
| | | | | | | | | This option allows the user to specify the use of absolute jumptables instead of relative which is the default on most PPC subtargets. Patch by Kamauu Bridgeman Differential revision: https://reviews.llvm.org/D69108
* [PowerPC] Fix the incorrect 'RM' flag set on load/store instrQingShan Zhang2019-11-061-0/+9
| | | | | | The 'RM' flag model the "Rounding Mode" and it has nothing to do with the load/store instructions. Differential Revision: https://reviews.llvm.org/D69551
* [MachineScheduler] Enable AA in PostRA Machine schedulerDavid Green2019-11-055-46/+46
| | | | | | | | | | | | This adds AA to Post-RA Machine Scheduling, allowing the pass more freedom when handling memory operations. My understanding is that this was just never done, not that it is inherently incorrect to do so. The older PostRA List scheduler already makes use of AA, it's just that the MI PostRA Scheduler was never taught to use it. Differential Revision: https://reviews.llvm.org/D69814
* Lower generic MASSV entries to PowerPC subtarget-specific entriesJinsong Ji2019-11-042-0/+632
| | | | | | | | | | | | | | | | | | | | | This patch (second of two patches) lowers the generic PowerPC vector entries to PowerPC subtarget-specific entries. For instance, the PowerPC generic entry 'cbrtd2_massv' is lowered to 'cbrtd2_P9' or Power9 subtarget. The first patch enables the vectorizer to recognize the IBM MASS vector library routines. This patch specifically adds support for recognizing the '-vector-library=MASSV' option, and defines mappings from IEEE standard scalar math functions to generic PowerPC MASS vector counterparts. For instance, the generic PowerPC MASS vector entry for double-precision 'cbrt' function is '__cbrtd2_massv' The overall support for MASS vector library is presented as such in two patches for ease of review. Patch by pjeeva01 (Jeeva P.) Differential Revision: https://reviews.llvm.org/D59883
* [LDV][RAGreedy] Inform LiveDebugVariables about new VRegs added by InlineSpillerBjorn Pettersson2019-11-011-0/+74
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: Make sure RAGreedy informs LiveDebugVariables about new VRegs that is introduced at spill by InlineSpiller. Consider this example LDV: !"var" [48r;128r):0 Loc0=%2 48B %2 = ... ... 128B %7 = ADD %2, ... If %2 is spilled the InlineSpiller will insert spill/reload instructions and introduces some new vregs. So we get 48B %4 = ... 56B spill %4 ... 120B reload %5 128B %3 = ADD %5, ... In the past we did not inform LDV about this, and when reintroducing DBG_VALUE instruction LDV still got information that "var" had the location of the spilled register %2 for the interval [48r;128r). The result was bad, since we mapped "var" to the spill slot even before the spill happened: %4 = ... DBG_VALUE %spill.0, !"var" spill %4 to %spill.0 ... reload %5 %3 = ADD %5, ... This patch will inform LDV about the interval split introduced due to spilling. So the location map in LDV will become !"var" [48r;56r):1 [56r;120r):0 [120r;128r):2 Loc0=%2 Loc1=%4 Loc2=%5 And when inserting DBG_VALUE instructions we get %4 = ... DBG_VALUE %4, !"var" spill %4 to %spill.0 DBG_VALUE %spill.0, !"var" ... reload %5 DBG_VALUE %5, !"var" %3 = ADD %5, ... Fixes: https://bugs.llvm.org/show_bug.cgi?id=38899 Reviewers: jmorse, vsk, aprantl Reviewed By: jmorse Subscribers: dstenb, wuzish, MatzeB, qcolombet, nemanjai, hiraditya, jsji, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D69584
* [PowerPC][AIX] Adds support for writing the data section in object filesjasonliu2019-10-302-224/+460
| | | | | | | | | | | | | | | | | | | | Adds support for generating the XCOFF data section in object files for global variables with initialization. Merged aix-xcoff-common.ll into aix-xcoff-data.ll. Changed variable name charr to chrarray in the test case to test if readobj works with 8-character names. Authored by: xingxue Reviewers: hubert.reinterptrtcast, sfertile, jasonliu, daltenty, Xiangling_L. Reviewed by: hubert.reinterpretcast, sfertile, daltenty. Subscribers: DiggerLin, Wuzish, nemanjai, hiraditya, MaskRay, jsji, shchenz, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D67125
* [AIX] Lowering CPI/JTI/BA to MIRXiangling Liao2019-10-303-0/+132
| | | | | | Enable lowering of constant pool index, jump table index, and bloack address to MIR on AIX. Differential Revision: https://reviews.llvm.org/D69264
* [PowerPC] Clear the sideeffect bit for those instructions that didn't have ↵QingShan Zhang2019-10-302-10/+49
| | | | | | | | | | | | the match pattern If the instruction have match pattern, llvm-tblgen will infer the sideeffect bit from the match pattern and it works well. If not, the tblgen will set it as true that hurt the scheduling. PowerPC has some instructions that didn't specify the match pattern(i.e. LXSD etc), which is manually selected post-ra according to the register pressure. We need to clear the sideeffect flag for these instructions. Differential Revision: https://reviews.llvm.org/D69232
* [X86] Make memcmp vector lowering handle arbitrary expansionsDavid Zarzycki2019-10-301-4/+4
| | | | | | | | | | Teach combineVectorSizedSetCCEquality() to handle arbitrary memcmp expansions but do not change any default policy for now. This also fixes a bug in the memcmp expansion itself when large displacements are needed. https://reviews.llvm.org/D69507
* [PowerPC] Emit scalar fp min/max instructionsNemanja Ivanovic2019-10-282-20/+223
| | | | | | | | | | VSX provides floating point minimum and maximum instructions that conform to IEEE semantics. This legalizes the respective nodes and emits VSX code for them. Furthermore, on Power9 cores we have xsmaxcdp and xsmincdp instructions that conform to language semantics for the conditional operator even in the presence of NaNs. Differential revision: https://reviews.llvm.org/D62993
* [PowerPC] Do not emit HW loop if the body contains calls to lrint/lroundNemanja Ivanovic2019-10-281-0/+75
| | | | | | | | These two intrinsics are lowered to calls so should prevent the formation of CTR loops. In a subsequent patch, we will handle all currently known intrinsics and prevent the formation of HW loops if any unknown intrinsics are encountered. Differential revision: https://reviews.llvm.org/D68841
* [AIX] Refactor AIX Call Lowering to use CCState. NFCI.Sean Fertile2019-10-284-0/+56
| | | | | | | | | | | | | This patch reworks the AIX call lowering to use CCState. Some defensive errors are added in this patch to protect from emitting bad code for calling convention logic that has not been implemented by design. The use of CCState follows the precedent of other targets and enables the reuse of calling convention logic in LowerFormalArguments, which will be rewritten to also use CCState in a late patch. Patch by Chris Bowler. Differential Revision: https://reviews.llvm.org/D69101
* [DAGCombiner] widen any_ext of popcount based on target supportSanjay Patel2019-10-282-8/+8
| | | | | | | | | This enhances D69127 (rGe6c145e0548e3b3de6eab27e44e1504387cf6b53) to handle the looser "any_extend" cast in addition to zext. This is a prerequisite step for canonicalizing in the other direction (narrow the popcount) in IR - PR43688: https://bugs.llvm.org/show_bug.cgi?id=43688
* [DAGCombiner] widen zext of popcount based on target supportSanjay Patel2019-10-251-9/+6
| | | | | | | | | | | | | | | | zext (ctpop X) --> ctpop (zext X) This is a prerequisite step for canonicalizing in the other direction (narrow the popcount) in IR - PR43688: https://bugs.llvm.org/show_bug.cgi?id=43688 I'm not sure if any other targets are affected, but I found a missing fold for PPC, so added tests based on that. The reason we widen all the way to 64-bit in these tests is because the initial DAG looks something like this: t5: i8 = ctpop t4 t6: i32 = zero_extend t5 <-- created based on IR, but unused node? t7: i64 = zero_extend t5 Differential Revision: https://reviews.llvm.org/D69127
* [PowerPC] add test for popcnt with any_extend; NFCSanjay Patel2019-10-251-1/+39
| | | | A zext-specific variation of this case is proposed in D69127.
* [PowerPC] [Peephole] fold frame offset by using index form to save add.czhengsz2019-10-251-6/+46
| | | | | | | | | | | | | | | | renamable $x6 = ADDI8 $x1, -80 ;;; 0 is replaced with -80 renamable $x6 = ADD8 killed renamable $x6, renamable $x5 STW killed renamable $r3, 4, killed renamable $x6 :: (store 4 into %ir.14, !tbaa !2) After PEI there is a peephole opt opportunity to combine above -80 in ADDI8 with 4 in the STW to eliminate unnecessary ADD8. Expected result: renamable $x6 = ADDI8 $x1, -76 STWX killed renamable $r3, renamable $x5, killed renamable $x6 :: (store 4 into %ir.6, !tbaa !2) Reviewed by: stefanp Differential Revision: https://reviews.llvm.org/D66329
* Test commit via git.Kai Luo2019-10-251-0/+1
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* [PowerPC][NFC] Remove deprecated Function Attrs comments #2Jinsong Ji2019-10-221-3/+3
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* [PowerPC][NFC] Remove deprecated Function Attrs commentsJinsong Ji2019-10-221-129/+2
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* [PowerPC] Turn on CR-Logical reducer passNemanja Ivanovic2019-10-225-45/+52
| | | | | | | | | | | | | | This re-commits r375152 which was pulled in r375233 because it broke the EXPENSIVE_CHECKS bot on Windows. The reason for the failure was a bug in the pass that the commit turned on by default. This patch fixes that bug and turns the pass back on. This patch has been verified on the buildbot that originally failed thanks to Simon Pilgrim. Differential revision: https://reviews.llvm.org/D52431 llvm-svn: 375497
* [PowerPC] Regenerate test for D52431Simon Pilgrim2019-10-211-7/+19
| | | | llvm-svn: 375435
* Revert r375152 as it is causing failures on EXPENSIVE_CHECKS botNemanja Ivanovic2019-10-185-65/+46
| | | | llvm-svn: 375233
* [PowerPC] Turn on CR-Logical reducer passNemanja Ivanovic2019-10-175-46/+65
| | | | | | | | | | | | | | | | | Quite a while ago, we implemented a pass that will reduce the number of CR-logical operations we emit. It does so by converting a CR-logical operation into a branch. We have kept this off by default because it seemed to cause a significant regression with one benchmark. However, that regression turned out to be due to a completely unrelated reason - AADB introducing a self-copy that is a priority-setting nop and it was just exacerbated by this pass. Now that we understand the reason for the only degradation, we can turn this pass on by default. We have long since fixed the cause for the degradation. Differential revision: https://reviews.llvm.org/D52431 llvm-svn: 375152
* [PowerPC] add tests for popcount with zext; NFCSanjay Patel2019-10-171-0/+304
| | | | llvm-svn: 375142
* [AIX] TOC pseudo expansion for 64bit large + 64bit small + 32bit large modelsXiangling Liao2019-10-172-12/+81
| | | | | | | | | This patch provides support for peudo ops including ADDIStocHA8, ADDIStocHA, LWZtocL, LDtoc, LDtocL for AIX, lowering them from MIR to assembly. Differential Revision: https://reviews.llvm.org/D68341 llvm-svn: 375113
* [XCOFF] Output object text section header and symbol entry for program code.Digger Lin2019-10-152-14/+22
| | | | | | | | | | | | | | | | | | | | | | | | | This is remaining part of rG41ca91f2995b: [AIX][XCOFF] Output XCOFF object text section header and symbol entry for rogram code. SUMMARY: Original form of this patch is provided by Stefan Pintillie. 1. The patch try to output program code section header , symbol entry for program code (PR) and Instruction into the raw text section. 2. The patch include how to alignment and layout the CSection in the text section. 3. The patch also reorganize the code , put some codes into a function. (XCOFFObjectWriter::writeSymbolTableEntryForControlSection) Additional: We can not add raw data of text section test in the patch, If want to output raw text section data,it need a function description patch first. Reviewers: hubert.reinterpretcast, sfertile, jasonliu, xingxue. Subscribers: wuzish, nemanjai, hiraditya, MaskRay, jsjji. Differential Revision: https://reviews.llvm.org/D66969 llvm-svn: 374923
* [AIX][XCOFF] Output XCOFF object text section header and symbol entry for ↵Digger Lin2019-10-151-0/+11
| | | | | | | | | | | | | | | | | | | program code. SUMMARY Original form of this patch is provided by Stefan Pintillie. The patch try to output program code section header , symbol entry for program code (PR) and Instruction into the raw text section. The patch include how to alignment and layout the CSection in the text section. The patch also reorganize the code , put some codes into a function(XCOFFObjectWriter::writeSymbolTableEntryForControlSection) Additional: We can not add raw data of text section test in the patch, If want to output raw text section data,it need a function description patch first. Reviewers: hubert.reinterpretcast, sfertile, jasonliu, xingxue. Subscribers: wuzish, nemanjai, hiraditya, MaskRay, jsjji. Differential Revision: https://reviews.llvm.org/D66969 llvm-svn: 374914
* [DebugInfo] Remove some users of DBG_VALUEs IsIndirect fieldJeremy Morse2019-10-151-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch kills off a significant user of the "IsIndirect" field of DBG_VALUE machine insts. Brought up in in PR41675, IsIndirect is techncally redundant as it can be expressed by the DIExpression of a DBG_VALUE inst, and it isn't helpful to have two ways of expressing things. Rather than setting IsIndirect, have DBG_VALUE creators add an extra deref to the insts DIExpression. There should now be no appearences of IsIndirect=True from isel down to LiveDebugVariables / VirtRegRewriter, which is ensured by an assertion in LDVImpl::handleDebugValue. This means we also get to delete the IsIndirect handling in LiveDebugVariables. Tests can be upgraded by for example swapping the following IsIndirect=True DBG_VALUE: DBG_VALUE $somereg, 0, !123, !DIExpression(DW_OP_foo) With one where the indirection is in the DIExpression, by _appending_ a deref: DBG_VALUE $somereg, $noreg, !123, !DIExpression(DW_OP_foo, DW_OP_deref) Which both mean the same thing. Most of the test changes in this patch are updates of that form; also some changes in how the textual assembly printer handles these insts. Differential Revision: https://reviews.llvm.org/D68945 llvm-svn: 374877
* [AIX] Use .space instead of .zero in assemblyDavid Tenty2019-10-111-0/+17
| | | | | | | | | | | | | | Summary: The AIX system assembler does not understand .zero, so we should prefer emitting .space. Subscribers: nemanjai, hiraditya, kbarton, MaskRay, jsji, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D68815 llvm-svn: 374564
* [PowerPC] Remove assertion "Shouldn't overwrite a register before it is killed"Yi-Hong Lyu2019-10-111-0/+22
| | | | | | | | | | | | | | The assertion is everzealous and fail tests like: renamable $x3 = LI8 0 STD renamable $x3, 16, $x1 renamable $x3 = LI8 0 Remove the assertion since killed flag of $x3 is not mandentory. Differential Revision: https://reviews.llvm.org/D68344 llvm-svn: 374515
* [PowerPC] add testcase for ppc loop instr form prep - NFCChen Zheng2019-10-101-0/+753
| | | | llvm-svn: 374273
* [NFC][CGP] Tests for making ICMP_EQ use CR result of ICMP_S(L|G)T dominatorsYi-Hong Lyu2019-10-071-232/+260
| | | | llvm-svn: 373876
* [SelectionDAG] Add tests for LKK algorithmDavid Bolvansky2019-10-054-0/+3268
| | | | | | | | | | Added some tests testing urem and srem operations with a constant divisor. Patch by TG908 (Tim Gymnich) Differential Revision: https://reviews.llvm.org/D68421 llvm-svn: 373830
* Revert [CodeGen] Do the Simple Early Return in block-placement pass to ↵Reid Kleckner2019-10-041-4/+8
| | | | | | | | | | | | | | optimize the blocks This reverts r371177 (git commit f879c6875563c0a8cd838f1e13b14dd33558f1f8) It caused PR43566 by removing empty, address-taken MachineBasicBlocks. Such blocks may have references from blockaddress or other operands, and need more consideration to be removed. See the PR for a test case to use when relanding. llvm-svn: 373805
* [FPEnv] Strict FP tests should use the requisite function attributes.Kevin P. Neal2019-10-042-239/+242
| | | | | | | | | | | | | | | A set of function attributes is required in any function that uses constrained floating point intrinsics. None of our tests use these attributes. This patch fixes this. These tests have been tested against the IR verifier changes in D68233. Reviewed by: andrew.w.kaylor, cameron.mcinally, uweigand Approved by: andrew.w.kaylor Differential Revision: https://reviews.llvm.org/D67925 llvm-svn: 373761
* [PowerPC] Adjust the naming and operand order of fnmsub patternsJinsong Ji2019-10-035-5/+3
| | | | | | | | | | | | | | | | | | | | | | Summary: This is follow up patch of https://reviews.llvm.org/D67595. Adjust naming and the Commutable operands for additional patterns to make it easier to read. The testcase update also show that we can save some unecessary fmr as well. Reviewers: #powerpc, steven.zhang, hfinkel, nemanjai Reviewed By: #powerpc, nemanjai Subscribers: wuzish, hiraditya, kbarton, MaskRay, shchenz, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D68112 llvm-svn: 373652
* [PowerPC] Fix SH field overflow issueYi-Hong Lyu2019-10-021-0/+58
| | | | | | | | | | Store rlwinm Rx, Ry, 32, 0, 31 as rlwinm Rx, Ry, 0, 0, 31 and store rldicl Rx, Ry, 64, 0 as rldicl Rx, Ry, 0, 0. Otherwise SH field is overflow and fails assertion in assembly printing stage. Differential Revision: https://reviews.llvm.org/D66991 llvm-svn: 373519
* [PowerPC] make tests immune to improved undef handlingSanjay Patel2019-09-282-9/+9
| | | | | | | | | The fma mutate test will not exercise what it was intended to test once we simplify those ops immediately, but the test will still pass with the existing CHECKs, so I'm leaving it in case that still has minimal value. llvm-svn: 373149
* [AIX]Emit function descriptor csect in assemblyXiangling Liao2019-09-262-0/+76
| | | | | | | | | This patch emits the function descriptor csect for functions with definitions under both 32-bit/64-bit mode on AIX. Differential Revision: https://reviews.llvm.org/D66724 llvm-svn: 373009
* [PowerPC] Add missing pattern for VSX Scalar Negative Multiply-Subtract ↵Jinsong Ji2019-09-261-2/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Single Precision Summary: This was found during review of https://reviews.llvm.org/D66050. In the simple test of fdiv, we miss to fold ``` fneg 2, 2 xsmaddasp 3, 2, 0 ``` to ``` xsnmsubasp 3, 2, 0 ``` We have the patterns for Double Precision and vectors, just missing Single Precision, the patch add that. Reviewers: #powerpc, hfinkel, nemanjai, steven.zhang Reviewed By: #powerpc, steven.zhang Subscribers: wuzish, hiraditya, kbarton, MaskRay, shchenz, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D67595 llvm-svn: 372985
* Extends the expansion of the LWZtoc pseduo op for AIX.Sean Fertile2019-09-241-0/+21
| | | | | | Differential Revision: https://reviews.llvm.org/D67853 llvm-svn: 372772
* [NFC][PowerPC] Consolidate testing of common linkage symbolsJinsong Ji2019-09-2093-110/+155
| | | | | | | Add a new file to test the code gen for common linkage symbol. Remove common linkage in some other testcases to avoid distraction. llvm-svn: 372426
* [NFC][PowerPC] Fast-isel VSX support testJinsong Ji2019-09-194-15/+8
| | | | | | | We have fixed most of the VSX limitation in Fast-isel, so we can remove the -mattr=-vsx for most testcases now. llvm-svn: 372345
* [PowerPC] Exploit single instruction load-and-splat for word and doublewordNemanja Ivanovic2019-09-176-45/+284
| | | | | | | | | | | We currently produce a load, followed by (possibly a move for integers and) a splat as separate instructions. VSX has always had a splatting load for doublewords, but as of Power9, we have it for words as well. This patch just exploits these instructions. Differential revision: https://reviews.llvm.org/D63624 llvm-svn: 372139
* [PowerPC] Cust lower fpext v2f32 to v2f64 from extract_subvector v4f32Lei Huang2019-09-161-0/+87
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This is a follow up patch from https://reviews.llvm.org/D57857 to handle extract_subvector v4f32. For cases where we fpext of v2f32 to v2f64 from extract_subvector we currently generate on P9 the following: lxv 0, 0(3) xxsldwi 1, 0, 0, 1 xscvspdpn 2, 0 xxsldwi 3, 0, 0, 3 xxswapd 0, 0 xscvspdpn 1, 1 xscvspdpn 3, 3 xscvspdpn 0, 0 xxmrghd 0, 0, 3 xxmrghd 1, 2, 1 stxv 0, 0(4) stxv 1, 0(5) This patch custom lower it to the following sequence: lxv 0, 0(3) # load the v4f32 <w0, w1, w2, w3> xxmrghw 2, 0, 0 # Produce the following vector <w0, w0, w1, w1> xxmrglw 3, 0, 0 # Produce the following vector <w2, w2, w3, w3> xvcvspdp 2, 2 # FP-extend to <d0, d1> xvcvspdp 3, 3 # FP-extend to <d2, d3> stxv 2, 0(5) # Store <d0, d1> (%vecinit11) stxv 3, 0(4) # Store <d2, d3> (%vecinit4) Differential Revision: https://reviews.llvm.org/D61961 llvm-svn: 372029
* [PowerPC][NFC] Add a testcase for fdiv expansion.Jinsong Ji2019-09-151-0/+16
| | | | | | Pre-commit for following patch. llvm-svn: 371938
* [PowerPC][NFC] Move codegen tests to PowerPC from MIR/PowerPCJinsong Ji2019-09-134-0/+444
| | | | | | | | | | | | | All tests with -run-pass !=none should not in MIR/, See MIR/README. ``` Tests for codegen passes should NOT be here but in test/CodeGen/sometarget. As a rule of thumb this directory should only contain tests using 'llc -run-pass none'. ``` llvm-svn: 371857
* [PowerPC] Remove the SPE4RC register class and instead add f32 to the GPRC ↵Craig Topper2019-09-122-16/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | register class. Summary: Since the SPE4RC register class contains an identical set of registers and an identical spill size to the GPRC class its slightly confusing the tablegen emitter. It's preventing the GPRC_and_GPRC_NOR0 synthesized register class from inheriting VTs and AltOrders from GPRC or GPRC_NOR0. This is because SPE4C is found first in the super register class list when inheriting these properties and it doesn't set the VTs or AltOrders the same way as GPRC or GPRC_NOR0. This patch replaces all uses of GPE4RC with GPRC and allows GPRC and GPRC_NOR0 to contain f32. The test changes here are because the AltOrders are being inherited to GPRC_NOR0 now. Found while trying to determine if getCommonSubClass needs to take a VT argument. It was originally added to support fp128 on x86-64, I've changed some things about that so that it might be needed anymore. But a PowerPC test crashed without it and I think its due to this subclass issue. Reviewers: jhibbits, nemanjai, kbarton, hfinkel Subscribers: wuzish, nemanjai, mehdi_amini, hiraditya, kbarton, MaskRay, dexonsmith, jsji, shchenz, steven.zhang, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D67513 llvm-svn: 371779
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