bcm5719-llvm - Project Ortega BCM5719 LLVM

	Commit message (Collapse)	Author	Age	Files	Lines
*	NFC - Various typo fixes in tests	Gabor Buella	2018-07-04	1	-1/+1
\| \| \| \|	llvm-svn: 336268
*	Adding -verify-machineinstrs option to PowerPC tests	Ehsan Amiri	2016-08-03	1	-2/+2
\| \| \| \| \| \| \| \| \| \| \|	Currently we have a number of tests that fail with -verify-machineinstrs. To detect this cases earlier we add the option to the testcases with the exception of tests that will currently fail with this option. PR 27456 keeps track of this failures. No code review, as discussed with Hal Finkel. llvm-svn: 277624
*	While reviewing the changes to Clang to add builtin support for the vsld, ↵	Kit Barton	2015-03-05	1	-5/+8
\| \| \| \| \| \|	vsrd, and vsrad instructions, it was pointed out that the builtins are generating the LLVM opcodes (shl, lshr, and ashr) not calls to the intrinsics. This patch changes the implementation of the vsld, vsrd, and vsrad instructions from from intrinsics to VXForm_1 instructions and makes them legal with P8 Altivec. It also removes the definition of the int_ppc_altivec_vsld, int_ppc_altivec_vsrd, and int_ppc_altivec_vsrad intrinsics. llvm-svn: 231378
*	Add the following 64-bit vector integer arithmetic instructions added in POWER8:	Kit Barton	2015-03-03	1	-0/+33
	vaddudm vsubudm vmulesw vmulosw vmuleuw vmulouw vmuluwm vmaxsd vmaxud vminsd vminud vcmpequd vcmpequd. vcmpgtsd vcmpgtsd. vcmpgtud vcmpgtud. vrld vsld vsrd vsrad Phabricator review: http://reviews.llvm.org/D7959 llvm-svn: 231115