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* [mips] Split large test file into 3 smaller ones.Vasileios Kalintiris2016-02-014-712/+772
| | | | | | | Remove the old select.ll file and use select-int.ll, select-flt.ll, select-dbl.ll for testing selects on integers, floats & doubles respectivelly. llvm-svn: 259361
* [mips] Never select JAL for calls to an absolute immediate address.Daniel Sanders2016-01-111-0/+15
| | | | | | | | | | | | | | | Summary: It actually takes an offset into the current PC-region. This fixes the 'expr' command in lldb. Reviewers: vkalintiris, jaydeep, bhushan Subscribers: dsanders, llvm-commits Differential Revision: http://reviews.llvm.org/D16054 llvm-svn: 257339
* Use TargetRegisterInfo for printing MachineOperand register commentsDan Gohman2015-11-171-2/+2
| | | | | | | | | | | | | | | | Several places in AsmPrinter.cpp print comments describing MachineOperand registers using MCRegisterInfo, which uses MCOperand-oriented names. This doesn't work for targets that use virtual registers exclusively, as WebAssembly does, since virtual registers are represented and printed differently. This patch preserves what seems to be the spirit of r229978, avoiding the use of TM.getSubtargetImpl(), while still using MachineOperand-oriented printing for MachineOperands. Differential Revision: http://reviews.llvm.org/D14709 llvm-svn: 253338
* [mips] Define patterns for the atomic_{load,store}_{8,16,32,64} nodes.Vasileios Kalintiris2015-11-063-0/+110
| | | | | | | | | | | | | | | | Summary: Without these patterns we would generate a complete LL/SC sequence. This would be problematic for memory regions marked as WRITE-only or READ-only, as the instructions LL/SC would read/write to the protected memory regions correspondingly. Reviewers: dsanders Subscribers: llvm-commits, dsanders Differential Revision: http://reviews.llvm.org/D14397 llvm-svn: 252293
* [mips] Handle undef when extracting subregs from FP64 registers.Daniel Sanders2015-10-121-0/+14
| | | | | | | | | | | | | | | Summary: This removes unnecessary instructions when extracting from an undefined register and also fixes a crash for O32 when passing undef to a double argument in held in integer registers. Reviewers: vkalintiris Subscribers: llvm-commits, zoran.jovanovic, petarj Differential Revision: http://reviews.llvm.org/D13467 llvm-svn: 250039
* [mips][microMIPS] Fix an issue with selecting sqrt instruction in LLVM backendDaniel Sanders2015-10-061-0/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: This fixes 7 tests during fast LLVM test-suite run: * MultiSource/Benchmarks/McCat/18-imp/imp * MultiSource/Applications/oggenc/oggenc * MultiSource/Benchmarks/MallocBench/gs/gs * MultiSource/Benchmarks/MiBench/automotive-susan/automotive-susan * MultiSource/Benchmarks/VersaBench/beamformer/beamformer * MultiSource/Benchmarks/MiBench/consumer-lame/consumer-lame * MultiSource/Benchmarks/Bullet/bullet Error message was in the form of: fatal error: error in backend: Cannot select: 0x95c3288: f32 = fsqrt 0x95c0190 [ORD=9] [ID=18] 0x95c0190: f32 = fadd 0x95bef30, 0x95c4d00 [ORD=8] [ID=17] 0x95bef30: f32 = fmul 0x95c4988, 0x95c4988 [ORD=5] [ID=16] ... There was problem with selecting sqrt instruction in LLVM backend. To fix the issue changes are made in TableGen definition for sqrt instruction in MipsInstrFPU.td and new test file sqrt.ll is added to LLVM regression tests. Patch by Zlatko Buljan Reviewers: zoran.jovanovic, hvarga, dsanders Subscribers: llvm-commits, petarj Differential Revision: http://reviews.llvm.org/D13235 llvm-svn: 249416
* Revert r249123 - [mips][microMIPS] Fix an issue with selecting sqrt ↵Daniel Sanders2015-10-061-13/+0
| | | | | | | | instruction in LLVM backend The author was not credited and most of the commit message is missing. Will re-commit with this fixed. llvm-svn: 249415
* [mips][microMIPS] Fix an issue with selecting sqrt instruction in LLVM backendZoran Jovanovic2015-10-021-0/+13
| | | | | | Differential Revision: http://reviews.llvm.org/D13235 llvm-svn: 249123
* Fix vector splitting for extract_vector_elt and vector elements of <8-bits.Daniel Sanders2015-09-091-0/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: One of the vector splitting paths for extract_vector_elt tries to lower: define i1 @via_stack_bug(i8 signext %idx) { %1 = extractelement <2 x i1> <i1 false, i1 true>, i8 %idx ret i1 %1 } to: define i1 @via_stack_bug(i8 signext %idx) { %base = alloca <2 x i1> store <2 x i1> <i1 false, i1 true>, <2 x i1>* %base %2 = getelementptr <2 x i1>, <2 x i1>* %base, i32 %idx %3 = load i1, i1* %2 ret i1 %3 } However, the elements of <2 x i1> are not byte-addressible. The result of this is that the getelementptr expands to '%base + %idx * (1 / 8)' which simplifies to '%base + %idx * 0', and then simply '%base' causing all values of %idx to extract element zero. This commit fixes this by promoting the vector elements of <8-bits to i8 before splitting the vector. This fixes a number of test failures in pocl. Reviewers: pekka.jaaskelainen Subscribers: pekka.jaaskelainen, llvm-commits Differential Revision: http://reviews.llvm.org/D12591 llvm-svn: 247128
* [mips] Reserve address spaces 1-255 for software use.Daniel Sanders2015-09-081-0/+12
| | | | | | | | | | | | Summary: And define them to have noop casts with address spaces 0-255. Reviewers: pekka.jaaskelainen Subscribers: pekka.jaaskelainen, llvm-commits Differential Revision: http://reviews.llvm.org/D12678 llvm-svn: 246990
* Revert r229675 - [mips] Avoid redundant sign extension of the result of ↵Vasileios Kalintiris2015-08-043-3/+13
| | | | | | | | | | | | | | | | binary bitwise instructions. It introduced two regressions on 64-bit big-endian targets running under N32 (MultiSource/Benchmarks/tramp3d-v4/tramp3d-v4, and MultiSource/Applications/kimwitu++/kc) The issue is that on 64-bit targets comparisons such as BEQ compare the whole GPR64 but incorrectly tell the instruction selector that they operate on GPR32's. This leads to the elimination of i32->i64 extensions that are actually required by comparisons to work correctly. There's currently a patch under review that fixes this problem. llvm-svn: 243984
* Revert r237789 - [mips] The naming convention for private labels is ABI ↵Daniel Sanders2015-05-205-68/+68
| | | | | | | | | dependant. It works, but I've noticed that I missed several callers of createMCAsmInfo() and many don't have a TargetMachine to provide. llvm-svn: 237792
* [mips] The naming convention for private labels is ABI dependant.Daniel Sanders2015-05-205-68/+68
| | | | | | | | | | | | | | | | | Summary: For N32/N64, private labels begin with '.L' but for O32 they begin with '$'. MCAsmInfo now has an initializer function which can be used to provide information from the TargetMachine to control the assembly syntax. Reviewers: vkalintiris Reviewed By: vkalintiris Subscribers: jfb, sandeep, llvm-commits, rafael Differential Revision: http://reviews.llvm.org/D9821 llvm-svn: 237789
* [mips] Correct 128-bit shifts on 64-bit targets.Daniel Sanders2015-04-293-12/+12
| | | | | | | | | | | | | | | | Summary: The existing code was correct for 32-bit GPR's but not 64-bit GPR's. It now accounts for both cases. Reviewers: vkalintiris Reviewed By: vkalintiris Subscribers: llvm-commits, mohit.bhakkad, sagar Differential Revision: http://reviews.llvm.org/D9337 llvm-svn: 236099
* [mips] Optimize code generation for 64-bit variable shift instructions.Vasileios Kalintiris2015-04-213-63/+58
| | | | | | | | | | | | | | | | Summary: The 64-bit version of the variable shift instructions uses the shift_rotate_reg class which uses a GPR32Opnd to specify the variable shift amount. With this patch we avoid the generation of a redundant SLL instruction for the variable shift instructions in 64-bit targets. Reviewers: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D7413 llvm-svn: 235376
* [mips] Add backend support for Mips32r[35] and Mips64r[35].Daniel Sanders2015-02-1817-103/+245
| | | | | | | | | | | | | | | | | Summary: These ISA's didn't add any instructions so they are almost identical to Mips32r2 and Mips64r2. Even the ELF e_flags are the same, However the ISA revision in .MIPS.abiflags is 3 or 5 respectively instead of 2. Reviewers: vmedic Reviewed By: vmedic Subscribers: tomatabacu, llvm-commits, atanasyan Differential Revision: http://reviews.llvm.org/D7381 llvm-svn: 229695
* [mips] Avoid redundant sign extension of the result of binary bitwise ↵Vasileios Kalintiris2015-02-183-13/+3
| | | | | | | | | | | | instructions. Reviewers: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D7581 llvm-svn: 229675
* [mips] Remove unused check prefix from tests. NFC.Daniel Sanders2015-02-042-18/+18
| | | | | | | | | | | | Reviewers: vmedic Reviewed By: vmedic Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D7376 llvm-svn: 228145
* [mips] Enable arithmetic and binary operations for the i128 data type.Vasileios Kalintiris2015-01-2613-16/+384
| | | | | | | | | | | | | | | | | | Summary: This patch adds support for some operations that were missing from 128-bit integer types (add/sub/mul/sdiv/udiv... etc.). With these changes we can support the __int128_t and __uint128_t data types from C/C++. Depends on D7125 Reviewers: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D7143 llvm-svn: 227089
* [mips] Add tests for bitwise binary and integer arithmetic operators.Vasileios Kalintiris2015-01-2612-0/+1241
| | | | | | | | | | Reviewers: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D7125 llvm-svn: 227087
* Revert "[mips] Fix assertion on i128 addition/subtraction on MIPS64"Vasileios Kalintiris2015-01-262-189/+0
| | | | | | | | This reverts commit r227003. Support for addition/subtraction and various other operations for the i128 data type will be added in a future commit based on the review D7143. llvm-svn: 227082
* [mips] Fix assertion on i128 addition/subtraction on MIPS64Daniel Sanders2015-01-242-0/+189
| | | | | | | | | | | | | | | | Summary: In addition to the included tests, this fixes test/CodeGen/Generic/i128-addsub.ll on a mips64 host. Reviewers: atanasyan, sagar, vmedic Reviewed By: vmedic Subscribers: sdkie, llvm-commits Differential Revision: http://reviews.llvm.org/D6610 llvm-svn: 227003
* [mips] Enable code generation for MIPS-III.Vasileios Kalintiris2014-12-121-93/+146
| | | | | | | | | | | | | | | | | | Summary: This commit enables the MIPS-III target and adds support for code generation of SELECT nodes. We have to use pseudo-instructions with custom inserters for these nodes as MIPS-III CPUs do not have conditional-move instructions. Depends on D6212 Reviewers: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D6464 llvm-svn: 224128
* [mips] Support SELECT nodes for targets that don't have conditional-move ↵Vasileios Kalintiris2014-12-121-0/+649
| | | | | | | | | | | | | | | | | | | | | | | | instructions. Summary: For Mips targets that do not have conditional-move instructions, ie. targets before MIPS32 and MIPS-IV, we have to insert a diamond control-flow pattern in order to support SELECT nodes. In order to do that, we add pseudo-instructions with a custom inserter that emits the necessary control-flow that selects the correct value. With this patch we add complete support for code generation of Mips-II targets based on the LLVM test-suite. Reviewers: dsanders Reviewed By: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D6212 llvm-svn: 224124
* [mips] Add preliminary support for the MIPS II target.Vasileios Kalintiris2014-11-111-0/+181
| | | | | | | | | | | | | | | | | | | Summary: This patch enables code generation for the MIPS II target. Pre-Mips32 targets don't have the MUL instruction, so we add the correspondent pattern that uses the MULT/MFLO combination in order to retrieve the product. This is WIP as we don't support code generation for select nodes due to the lack of conditional-move instructions. Reviewers: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D6150 llvm-svn: 221686
* [mips][mips64r6] Use JALR for indirect branches instead of JR (which is not ↵Daniel Sanders2014-07-092-11/+24
| | | | | | | | | | | | | | | | | available on MIPS32r6/MIPS64r6) Summary: This completes the change to use JALR instead of JR on MIPS32r6/MIPS64r6. Reviewers: jkolek, vmedic, zoran.jovanovic, dsanders Reviewed By: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D4269 llvm-svn: 212605
* [mips][mips64r6] Use JALR for returns instead of JR (which is not available ↵Daniel Sanders2014-07-091-22/+61
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | on MIPS32r6/MIPS64r6) Summary: RET, and RET_MM have been replaced by a pseudo named PseudoReturn. In addition a version with a 64-bit GPR named PseudoReturn64 has been added. Instruction selection for a return matches RetRA, which is expanded post register allocation to PseudoReturn/PseudoReturn64. During MipsAsmPrinter, this PseudoReturn/PseudoReturn64 are emitted as: - (JALR64 $zero, $rs) on MIPS64r6 - (JALR $zero, $rs) on MIPS32r6 - (JR_MM $rs) on microMIPS - (JR $rs) otherwise On MIPS32r6/MIPS64r6, 'jr $rs' is an alias for 'jalr $zero, $rs'. To aid development and review (specifically, to ensure all cases of jr are updated), these aliases are temporarily named 'r6.jr' instead of 'jr'. A follow up patch will change them back to the correct mnemonic. Added (JALR $zero, $rs) to MipsNaClELFStreamer's definition of an indirect jump, and removed it from its definition of a call. Note: I haven't accounted for MIPS64 in MipsNaClELFStreamer since it's doesn't appear to account for any MIPS64-specifics. The return instruction created as part of eh_return expansion is now expanded using expandRetRA() so we use the right return instruction on MIPS32r6/MIPS64r6 ('jalr $zero, $rs'). Also, fixed a misuse of isABI_N64() to detect 64-bit wide registers in expandEhReturn(). Reviewers: jkolek, vmedic, mseaborn, zoran.jovanovic, dsanders Reviewed By: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D4268 llvm-svn: 212604
* [mips] Add tests for the 'ret', 'call', and 'indirectbr' LLVM IR instruction.Daniel Sanders2014-07-043-0/+353
Summary: The tests in this directory are intended to test a single IR instruction with as few dependencies on other instructions as possible. The aim is to be very confident that each LLVM-IR instruction is implemented correctly and with the optimal sequence of instructions, as well as to make it easy to tell what is tested, and make it easier to bring up new ISA revisions in the future. This gives us a good foundation on which to test bigger things. These particular tests will allow testing that MIPS32r6/MIPS64r6 generate the correct return instruction for returns, calls, and indirect branches. This will be a bit tricky since the assembly text is identical but the instruction is actually different. On MIPS32r6/MIPS64r6 'jr $rs' has been removed in favour of the equivalent 'jalr $zero, $rs'. 'jr $rs' remains as an alias for 'jalr $zero, $rs'. Differential Revision: http://reviews.llvm.org/D4266 llvm-svn: 212345
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