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llvm-svn: 177327
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Apparently my final cleanup to use a relevant suffix for these tests before
committing r176831 caused them to stop running since lit wasn't configured to
run tests with that suffix in those directories (why don't we just have a
global suffix list?). So, add the suffix to the relevant directories & fix the
test that has bitrotted over the last week due to my debug info schema changes.
llvm-svn: 177315
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llvm-svn: 176831
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Patch by Job Noorman!
llvm-svn: 168440
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llvm-svn: 168439
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Patch by Job Noorman!
llvm-svn: 166108
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No changes to these patches, MRI needed to be notified when changing
uses into defs and vice versa.
llvm-svn: 161644
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These commits broke a number of buildbots.
llvm-svn: 161640
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Use a more conventional doubly linked list where the Prev pointers form
a cycle. This means it is no longer necessary to adjust the Prev
pointers when reallocating the VRegInfo array.
The test changes are required because the register allocation hint is
using the use-list order to break ties.
llvm-svn: 161633
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because
the old verifier just checked that something "was a pointer", but not that the pointee
was correct.
llvm-svn: 157544
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* Removed test/lib/llvm.exp - it is no longer needed
* Deleted the dg.exp reading code from test/lit.cfg. There are no dg.exp files
left in the test suite so this code is no longer required. test/lit.cfg is
now much shorter and clearer
* Removed a lot of duplicate code in lit.local.cfg files that need access to
the root configuration, by adding a "root" attribute to the TestingConfig
object. This attribute is dynamically computed to provide the same
information as was previously provided by the custom getRoot functions.
* Documented the config.root attribute in docs/CommandGuide/lit.pod
llvm-svn: 153408
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run with LIT now and now Dejagnu. dg.exp is no longer needed.
Patch reviewed by Daniel Dunbar. It will be followed by additional cleanup patches.
llvm-svn: 150664
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instead of 'volatile load', which is archaic.
llvm-svn: 145171
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as the Latency scheduler is going away.
llvm-svn: 142811
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llvm-svn: 130815
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have their low bits set to zero. This allows us to optimize
out explicit stack alignment code like in stack-align.ll:test4 when
it is redundant.
Doing this causes the code generator to start turning FI+cst into
FI|cst all over the place, which is general goodness (that is the
canonical form) except that various pieces of the code generator
don't handle OR aggressively. Fix this by introducing a new
SelectionDAG::isBaseWithConstantOffset predicate, and using it
in places that are looking for ADD(X,CST). The ARM backend in
particular was missing a lot of addressing mode folding opportunities
around OR.
llvm-svn: 125470
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message instead of creating DBG_VALUE for undefined value in reg0.
llvm-svn: 121059
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llvm-svn: 118107
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llvm-svn: 114354
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when needed. This fixes PR7001
llvm-svn: 102838
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llvm-svn: 102836
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llvm-svn: 102835
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llvm-svn: 100705
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those who don't build all targets.
llvm-svn: 100688
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otherwise msp430-as will silently miscompile the code (TI's assembler report an error though).
This fixes PR6349
llvm-svn: 97877
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CopyToReg/CopyFromReg/INLINEASM. These are annoying because
they have the same opcode before an after isel. Fix this by
setting their NodeID to -1 to indicate that they are selected,
just like what automatically happens when selecting things that
end up being machine nodes.
With that done, give IsLegalToFold a new flag that causes it to
ignore chains. This lets the HandleMergeInputChains routine be
the one place that validates chains after a match is successful,
enabling the new hotness in chain processing. This smarter
chain processing eliminates the need for "PreprocessRMW" in the
X86 and MSP430 backends and enables MSP to start matching it's
multiple mem operand instructions more aggressively.
I currently #if out the dead code in the X86 backend and MSP
backend, I'll remove it for real in a follow-on patch.
The testcase changes are:
test/CodeGen/X86/sse3.ll: we generate better code
test/CodeGen/X86/store_op_load_fold2.ll: PreprocessRMW was
miscompiling this before, we now generate correct code
Convert it to filecheck while I'm at it.
test/CodeGen/MSP430/Inst16mm.ll: Add a testcase for mem/mem
folding to make anton happy. :)
llvm-svn: 97596
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to adding them in a determinstic order (bottom up from
the root) based on the structure of the graph itself.
This updates tests for some random changes, interesting
bits: CodeGen/Blackfin/promote-logic.ll no longer crashes.
I have no idea why, but that's good right?
CodeGen/X86/2009-07-16-LoadFoldingBug.ll also fails, but
now compiles to have one fewer constant pool entry, making
the expected load that was being folded disappear. Since it
is an unreduced mass of gnast, I just removed it.
This fixes PR6370
llvm-svn: 97023
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llvm-svn: 96826
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This fixes PR6348
llvm-svn: 96734
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llvm-svn: 93555
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llvm-svn: 93501
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llvm-svn: 93468
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llvm-svn: 92740
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Patch by Sylve`re Teissier (sorry, ASCII only).
llvm-svn: 91988
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llvm-svn: 91931
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Based on the patch by Brian Lucas!
llvm-svn: 91175
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instruction. Patch inspired by Brian Lucas!
llvm-svn: 90819
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the problem only shows for msp430 and pic16 which is why it specifies
them using -march. But it is wrong to put such tests in CodeGen/Generic,
since not everyone builds these targets. Put a copy of the test in each
of the target test directories.
llvm-svn: 90005
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llvm-svn: 86471
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llvm-svn: 86466
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since the instruction might use the other result of different type.
llvm-svn: 86462
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llvm-svn: 86385
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llvm-svn: 86384
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llvm-svn: 86382
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selected.
Yay for ASCII graphics!
llvm-svn: 84808
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llvm-svn: 84776
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disable some tests until it will be clever enough to handle them.
llvm-svn: 84775
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llvm-svn: 84705
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llvm-svn: 83837
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llvm-svn: 83812
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