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* [RDF] Fix liveness propagation through shadowsKrzysztof Parzyszek2016-10-031-0/+73
| | | | | | | | Each shadow only represents data flow that is restricted to its reaching def. Propagating more than that could lead to spurious register liveness, resulting in extra (incorrectly) block live-ins. llvm-svn: 283143
* IfConversion: Add implicit uses for redefined regs with live subregistersKrzysztof Parzyszek2016-09-281-0/+50
| | | | | | | | | | Normally, if conversion would add implicit uses for redefined registers, e.g. R0<def> = add_if ..., R0<imp-use>. However, if only subregisters of R0 are known to be live but not R0 itself, such implicit uses will not be added, causing prior definitions of such subregisters and R0 itself to become dead. llvm-svn: 282626
* [Hexagon] segv while processing SUnit with nullNodePtrRon Lieberman2016-09-171-0/+202
| | | | | | Added BoundaryNode check to isBestZeroLatency function. llvm-svn: 281825
* This reapplies r281304. The issue was that I had missedSjoerd Meijer2016-09-141-25/+5
| | | | | | to copy the new isAdd field in the tablegen data structure. llvm-svn: 281447
* [Hexagon] Better handling of HVX vector loweringKrzysztof Parzyszek2016-09-131-0/+21
| | | | | | | - Expand SELECT_CC and BR_CC for vector types. - Implement TLI::isShuffleMaskLegal. llvm-svn: 281397
* [Hexagon] Clear the flow queue after visiting a single instructionKrzysztof Parzyszek2016-09-131-0/+47
| | | | llvm-svn: 281339
* Revert of r281304 as it is causing build bot failures in hexagonSjoerd Meijer2016-09-131-5/+25
| | | | | | | hwloop regression tests. These tests pass locally; will be investigating where these differences come from. llvm-svn: 281306
* This adds a new field isAdd to MCInstrDesc. The ARM and Hexagon instructionSjoerd Meijer2016-09-131-25/+5
| | | | | | | | | | | descriptions now tag add instructions, and the Hexagon backend is using this to identify loop induction statements. Patch by Sam Parker and Sjoerd Meijer. Differential Revision: https://reviews.llvm.org/D23601 llvm-svn: 281304
* [RDF] Further improve handling of multiple phis reached from shadowsKrzysztof Parzyszek2016-09-081-0/+40
| | | | llvm-svn: 280987
* [Hexagon] Expand sext- and zextloads of vector types, not just extloadsKrzysztof Parzyszek2016-09-081-0/+10
| | | | | | Recent change exposed this issue, breaking the Hexagon buildbots. llvm-svn: 280973
* [RDF] Fix liveness analysis for phi nodes with shadow usesKrzysztof Parzyszek2016-09-071-0/+64
| | | | | | | | Shadow uses need to be analyzed together, since each individual shadow will only have a partial reaching def. All shadows together may cover a given register ref, while each individual shadow may not. llvm-svn: 280855
* [RDF] Ignore undef use operandsKrzysztof Parzyszek2016-09-061-0/+55
| | | | llvm-svn: 280717
* [Hexagon] Deal with undefs when extending live intervalsKrzysztof Parzyszek2016-09-011-0/+112
| | | | | | Reapply r280275, since MSVC accepts r280358. llvm-svn: 280369
* Revert "Add an optional parameter with a list of undefs to extendToIndices"Reid Kleckner2016-08-311-112/+0
| | | | | | | | | | | | This reverts commit r280268, it causes all MSVC 2013 to ICE. This appears to have been fixed in a later MSVC 2013 update, because I cannot reproduce it locally. That said, all upstream LLVM bots are broken right now, so I am reverting. Also reverts dependent change r280275, "[Hexagon] Deal with undefs when extending live intervals". llvm-svn: 280301
* [Hexagon] Deal with undefs when extending live intervalsKrzysztof Parzyszek2016-08-311-0/+112
| | | | llvm-svn: 280275
* Fixed spill stack objects are mutableKrzysztof Parzyszek2016-08-311-0/+69
| | | | | | Differential Revision: https://reviews.llvm.org/D24039 llvm-svn: 280244
* Propagate TBAA info in SelectionDAG::getIndexedLoadKrzysztof Parzyszek2016-08-291-0/+37
| | | | | | Patch by Pranav Bhandarkar. llvm-svn: 279998
* IfConversion: Fix branch predication bug.Kyle Butt2016-08-291-0/+37
| | | | | | | | | | | | This bug shows up with diamonds that share unpredicable, unanalyzable branches. There's an included test case from Hexagon. What was happening was that we were attempting to predicate the branch instruction despite the fact that it was checked to be the same. Now for unanalyzable branches we skip over the branch instructions when predicating the block. Differential Revision: https://reviews.llvm.org/D23939 llvm-svn: 279985
* [Hexagon] vector store print tracing.Ron Lieberman2016-08-251-0/+5
| | | | | | | | Add vector store print tracing option for hexagon vector instructions. https://reviews.llvm.org/D23870 llvm-svn: 279739
* MachineFunctionProperties/MIRParser: Rename AllVRegsAllocated->NoVRegs, ↵Matthias Braun2016-08-251-1/+0
| | | | | | | | | | | | | compute it Rename AllVRegsAllocated to NoVRegs. This avoids the connotation of running after register and simply describes that no vregs are used in a machine function. With that we can simply compute the property and do not need to dump/parse it in .mir files. Differential Revision: http://reviews.llvm.org/D23850 llvm-svn: 279698
* [Hexagon] Check for block end when skipping debug instructionsKrzysztof Parzyszek2016-08-241-0/+57
| | | | llvm-svn: 279681
* Missed a test in my last commitMatthias Braun2016-08-241-1/+0
| | | | llvm-svn: 279679
* Create subranges for new intervals resulting from live interval splittingKrzysztof Parzyszek2016-08-241-0/+205
| | | | | | | | | | | | | | | | | | | The register allocator can split a live interval of a register into a set of smaller intervals. After the allocation of registers is complete, the rewriter will modify the IR to replace virtual registers with the corres- ponding physical registers. At this stage, if a register corresponding to a subregister of a virtual register is used, the rewriter will check if that subregister is undefined, and if so, it will add the <undef> flag to the machine operand. The function verifying liveness of the subregis- ter would assume that it is undefined, unless any of the subranges of the live interval proves otherwise. The problem is that the live intervals created during splitting do not have any subranges, even if the original parent interval did. This could result in the <undef> flag placed on a register that is actually defined. Differential Revision: http://reviews.llvm.org/D21189 llvm-svn: 279625
* [Hexagon] Packetize return value setup with the return instructionKrzysztof Parzyszek2016-08-231-0/+37
| | | | | | Commit r279241 unintentionally reverted that ability. llvm-svn: 279526
* [Hexagon] Add RUN line to testKrzysztof Parzyszek2016-08-191-0/+4
| | | | llvm-svn: 279304
* [Hexagon] Allow i1 values for 'r' constraint in inline-asmKrzysztof Parzyszek2016-08-191-0/+10
| | | | llvm-svn: 279302
* [Hexagon] Fixes for new-value jump formationKrzysztof Parzyszek2016-08-191-0/+63
| | | | | | | - Recognize C2_cmpgtui, S2_tstbit_i, and S4_ntstbit_i. - Avoid creating new-value instructions with both source operands equal. llvm-svn: 279286
* [Hexagon] Enforce LLSC packetization rulesKrzysztof Parzyszek2016-08-191-0/+12
| | | | | | | | | Ensure that load locked and store conditional instructions are only packetized with ALU32 instructions. Patch by Ben Craig. llvm-svn: 279272
* [Hexagon] Fix incorrect generation of S4_subi_asl_riKrzysztof Parzyszek2016-08-191-0/+70
| | | | | | Patch by Jyotsna Verma. llvm-svn: 279267
* [Hexagon] Allow tail-call optimization when mixing C and fast calling convKrzysztof Parzyszek2016-08-191-0/+22
| | | | | | Patch by Arnold Schwaighofer. llvm-svn: 279251
* [Hexagon] Check for empty live intervalKrzysztof Parzyszek2016-08-191-0/+47
| | | | | | Patch by Brendon Cahoon. llvm-svn: 279249
* [Hexagon] Mark PS_jumpret as pseudo-instruction, expand it into J2_jumprKrzysztof Parzyszek2016-08-191-4/+3
| | | | llvm-svn: 279241
* [Hexagon] Improvements to handling and generation of FP instructionsKrzysztof Parzyszek2016-08-193-0/+141
| | | | | | | | | Improved handling of fma, floating point min/max, additional load/store instructions for floating point types. Patch by Jyotsna Verma. llvm-svn: 279239
* [Hexagon] Create vcombine in HexagonCopyToCombineKrzysztof Parzyszek2016-08-181-0/+56
| | | | llvm-svn: 279067
* [Pipeliner] Fix an asssert due to invalid Phi in the epilogBrendon Cahoon2016-08-161-0/+44
| | | | | | | | | | | | The pipeliner was generating an invalid Phi name for an operand in the epilog block, which caused an assert in the live variable analysis pass. The fix is to the code that generates new Phis in the epilog block. In this case, there is an existing Phi that needs to be reused rather than creating a new Phi instruction. Differential Revision: https://reviews.llvm.org/D23513 llvm-svn: 278805
* [Hexagon] Improve test to check for @PCREL, only run llc, not opt -> llc.Ron Lieberman2016-08-161-2/+2
| | | | llvm-svn: 278796
* [LSR] Don't try and create post-inc expressions on non-rotated loopsJames Molloy2016-08-152-2/+1
| | | | | | | | | | | | | | | If a loop is not rotated (for example when optimizing for size), the latch is not the backedge. If we promote an expression to post-inc form, we not only increase register pressure and add a COPY for that IV expression but for all IVs! Motivating testcase: void f(float *a, float *b, float *c, int n) { while (n-- > 0) *c++ = *a++ + *b++; } It's imperative that the pointer increments be located in the latch block and not the header block; if not, we cannot use post-increment loads and stores and we have to keep both the post-inc and pre-inc values around until the end of the latch which bloats register usage. llvm-svn: 278658
* Fix unsupported relocation type R_HEX_6_X' for symbol .rodataRon Lieberman2016-08-131-0/+40
| | | | | | | | | | | LowerTargetConstantPool is not properly setting the TargetFlag to indicate desired relocation. Coding error, the offset parameter was omitted, so the TargetFlag was used as the offset, and the TargetFlag defaulted to zero. This only affects -fpic compilation, and only those items created in a Constant Pool, for example a vector of constants. Halide ran into this issue. llvm-svn: 278614
* [Hexagon] Allow non-returning calls in hardware loopsKrzysztof Parzyszek2016-08-111-0/+63
| | | | llvm-svn: 278416
* If-conversion incorrectly calculates liveness of redefined registersKrzysztof Parzyszek2016-08-111-0/+43
| | | | | | Differential Revision: https://reviews.llvm.org/D23207 llvm-svn: 278383
* [Hexagon] Skip byval arguments when checking parameter attributesKrzysztof Parzyszek2016-08-111-0/+11
| | | | | | | | | | From the point of view of register assignment, byval parameters are ignored: a byval parameter is not going to be assigned to a register, and it will not affect the assignments of subsequent parameters. When matching registers with parameters in the bit tracker, make sure to skip byval parameters before advancing the registers. llvm-svn: 278375
* Codegen: Tail Merge: Be less aggressive with special cases.Kyle Butt2016-08-101-1/+1
| | | | | | | | | | | | This change makes it possible for tail-duplication and tail-merging to be disjoint. By being less aggressive when merging during layout, there are no overlapping cases between tail-duplication and tail-merging, provided the thresholds are disjoint. There is a remaining TODO to benchmark the succ_size() test for non-layout tail merging. llvm-svn: 278265
* [Hexagon] Simplify the SplitConst32/64 passKrzysztof Parzyszek2016-08-101-7/+11
| | | | llvm-svn: 278256
* [Hexagon] Add extra patterns for single-precision min/max instructionsKrzysztof Parzyszek2016-08-101-0/+67
| | | | llvm-svn: 278252
* [Hexagon] Use integer instructions for floating point immediatesKrzysztof Parzyszek2016-08-101-0/+22
| | | | | | | | | | | | Floating point instructions use general purpose registers, so the few instructions that can put floating point immediates into registers are, in fact, integer instruction. Use them explicitly instead of having pseudo-instructions specifically for dealing with floating point values. Simplify the constant loading instructions (from sdata) to have only two: one for 32-bit values and one for 64-bit values: CONST32 and CONST64. llvm-svn: 278244
* [Hexagon] Add pattern for 64-bit mulhsKrzysztof Parzyszek2016-08-081-0/+23
| | | | llvm-svn: 278040
* [Hexagon] Validate register class when doing bit simplificationKrzysztof Parzyszek2016-08-041-0/+21
| | | | llvm-svn: 277740
* [Hexagon] Clear kill flags from modified registers in peephole optimizerKrzysztof Parzyszek2016-08-041-0/+27
| | | | llvm-svn: 277727
* [Hexagon] Generate COPY/REG_SEQUENCE more aggressively for vectorsKrzysztof Parzyszek2016-08-031-1/+1
| | | | llvm-svn: 277626
* [Hexagon] Do not check alignment for unsized types in isLegalAddressingModeKrzysztof Parzyszek2016-08-031-0/+58
| | | | | | | | When the same base address is used to load two different data types, LSR would assume a memory type of "void". This type is not sized and has no alignment information. Checking for it causes a crash. llvm-svn: 277601
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