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* [Hexagon] Add a few more lit testsKrzysztof Parzyszek2018-03-1918-1/+1652
| | | | llvm-svn: 327884
* [Hexagon] Avoid bank conflicts in post-RA schedulerKrzysztof Parzyszek2018-03-161-0/+156
| | | | | | | | | | Avoid scheduling two loads in such a way that they would end up in the same packet. If there is a load in a packet, try to schedule a non-load next. Patch by Brendon Cahoon. llvm-svn: 327742
* [Hexagon] Add lit testcases for atomic intrinsicsKrzysztof Parzyszek2018-03-163-0/+177
| | | | | | Patch by Ben Craig. llvm-svn: 327737
* [Hexagon] Fix zero-extending non-HVX bool vectorsKrzysztof Parzyszek2018-03-161-0/+69
| | | | llvm-svn: 327712
* [CodeGen] Use MIR syntax for MachineMemOperand printingFrancis Visoiu Mistrih2018-03-141-1/+1
| | | | | | | | | | Get rid of the "; mem:" suffix and use the one we use in MIR: ":: (load 2)". rdar://38163529 Differential Revision: https://reviews.llvm.org/D42377 llvm-svn: 327580
* [Hexagon] Fix typo in testcaseKrzysztof Parzyszek2018-03-121-1/+1
| | | | llvm-svn: 327310
* [Hexagon] Counting leading/trailing bits is cheapKrzysztof Parzyszek2018-03-121-0/+75
| | | | llvm-svn: 327308
* [Hexagon] Subtarget feature to emit one instruction per packetKrzysztof Parzyszek2018-03-122-0/+109
| | | | | | | | | | | | | | | | | This adds two features: "packets", and "nvj". Enabling "packets" allows the compiler to generate instruction packets, while disabling it will prevent it and disable all optimizations that generate them. This feature is enabled by default on all subtargets. The feature "nvj" allows the compiler to generate new-value jumps and it implies "packets". It is enabled on all subtargets. The exception is made for packets with endloop instructions, since they require a certain minimum number of instructions in the packets to which they apply. Disabling "packets" will not prevent hardware loops from being generated. llvm-svn: 327302
* [Hexagon] Add REQUIRES: asserts to testcases that use -statsKrzysztof Parzyszek2018-03-122-0/+2
| | | | llvm-svn: 327281
* [Hexagon] Add REQUIRES: asserts to testcases that use -debug-onlyKrzysztof Parzyszek2018-03-123-1/+3
| | | | llvm-svn: 327279
* [Hexagon] Add more lit testsKrzysztof Parzyszek2018-03-12386-0/+32789
| | | | llvm-svn: 327271
* [Hexagon] Ignore indexed loads when handling unaligned loadsKrzysztof Parzyszek2018-03-081-0/+67
| | | | llvm-svn: 327037
* [Pipeliner] Fixed node order issue related to zero latency edgesRoorda, Jan-Willem2018-03-074-7/+20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: A desired property of the node order in Swing Modulo Scheduling is that for nodes outside circuits the following holds: none of them is scheduled after both a successor and a predecessor. We call node orders that meet this property valid. Although invalid node orders do not lead to the generation of incorrect code, they can cause the pipeliner not being able to find a pipelined schedule for arbitrary II. The reason is that after scheduling the successor and the predecessor of a node, no room may be left to schedule the node itself. For data flow graphs with 0-latency edges, the node ordering algorithm of Swing Modulo Scheduling can generate such undesired invalid node orders. This patch fixes that. In the remainder of this commit message, I will give an example demonstrating the issue, explain the fix, and explain how the the fix is tested. Consider, as an example, the following data flow graph with all edge latencies 0 and all edges pointing downward. ``` n0 / \ n1 n3 \ / n2 | n4 ``` Consider the implemented node order algorithm in top-down mode. In that mode, the algorithm orders the nodes based on greatest Height and in case of equal Height on lowest Movability. Finally, in case of equal Height and Movability, given two nodes with an edge between them, the algorithm prefers the source-node. In the graph, for every node, the Height and Movability are equal to 0. As will be explained below, the algorithm can generate the order n0, n1, n2, n3, n4. So, node n3 is scheduled after its predecessor n0 and after its successor n2. The reason that the algorithm can put node n2 in the order before node n3, even though they have an edge between them in which node n3 is the source, is the following: Suppose the algorithm has constructed the partial node order n0, n1. Then, the nodes left to be ordered are nodes n2, n3, and n4. Suppose that the while-loop in the implemented algorithm considers the nodes in the order n4, n3, n2. The algorithm will start with node n4, and look for more preferable nodes. First, node n4 will be compared with node n3. As the nodes have equal Height and Movability and have no edge between them, the algorithm will stick with node n4. Then node n4 is compared with node n2. Again the Height and Movability are equal. But, this time, there is an edge between the two nodes, and the algorithm will prefer the source node n2. As there are no nodes left to compare, the algorithm will add node n2 to the node order, yielding the partial node order n0, n1, n2. In this way node n2 arrives in the node-order before node n3. To solve this, this patch introduces the ZeroLatencyHeight (ZLH) property for nodes. It is defined as the maximum unweighted length of a path from the given node to an arbitrary node in which each edge has latency 0. So, ZLH(n0)=3, ZLH(n1)=ZLH(n3)=2, ZLH(n2)=1, and ZLH(n4)=0 In this patch, the preference for a greater ZeroLatencyHeight is added in the top-down mode of the node ordering algorithm, after the preference for a greater Height, and before the preference for a lower Movability. Therefore, the two allowed node-orders are n0, n1, n3, n2, n4 and n0, n3, n1, n2, n4. Both of them are valid node orders. In the same way, the bottom-up mode of the node ordering algorithm is adapted by introducing the ZeroLatencyDepth property for nodes. The patch is tested by adding extra checks to the following existing lit-tests: test/CodeGen/Hexagon/SUnit-boundary-prob.ll test/CodeGen/Hexagon/frame-offset-overflow.ll test/CodeGen/Hexagon/vect/vect-shuffle.ll Before this patch, the pipeliner failed to pipeline the loops in these tests due to invalid node-orders. After the patch, the pipeliner successfully pipelines all these loops. Reviewers: bcahoon Reviewed By: bcahoon Subscribers: Ayal, mgrang, llvm-commits Differential Revision: https://reviews.llvm.org/D43620 llvm-svn: 326925
* [Hexagon] Rewrite non-HVX unaligned loads as pairs of aligned onesKrzysztof Parzyszek2018-03-074-6/+4
| | | | | | | | | This is a follow-up to r325169, this time for all types, not just HVX vector types. Disable this by default, since it's not always safe. llvm-svn: 326915
* [Hexagon] Update more testcasesKrzysztof Parzyszek2018-03-0634-112/+103
| | | | llvm-svn: 326830
* [Hexagon] Remove {{ *}} from testcasesKrzysztof Parzyszek2018-03-0630-198/+197
| | | | | | The spaces in the instructions are now consistent. llvm-svn: 326829
* [Hexagon] Generate valignb for shifting shuffles (instead of vdelta)Krzysztof Parzyszek2018-03-022-0/+2548
| | | | llvm-svn: 326627
* [Hexagon] Handle VACOPY in isel loweringKrzysztof Parzyszek2018-03-021-0/+18
| | | | llvm-svn: 326599
* [Hexagon] Recognize more sign-extensions as inputs to 32x32-bit multiplyKrzysztof Parzyszek2018-02-271-0/+28
| | | | llvm-svn: 326263
* [Pipeliner] Drop memrefs instead of creating ones with size UINT64_MAXKrzysztof Parzyszek2018-02-271-5/+5
| | | | | | | | | Absence of memory operands is treated as "aliasing everything", so dropping them is sufficient. Recommit r326256 with a fixed testcase. llvm-svn: 326262
* [Hexagon] Add patterns for compares of i1 valuesKrzysztof Parzyszek2018-02-271-0/+27
| | | | llvm-svn: 326220
* [CodeGen] Don't omit any redundant information in -debug outputFrancis Visoiu Mistrih2018-02-261-1/+1
| | | | | | | | | | | | | | | | | | | | | In r322867, we introduced IsStandalone when printing MIR in -debug output. The default behaviour for that was: 1) If any of MBB, MI, or MO are -debug-printed separately, don't omit any redundant information. 2) When -debug-printing a MF entirely, don't print any redundant information. 3) When printing MIR, don't print any redundant information. I'd like to change 2) to: 2) When -debug-printing a MF entirely, don't omit any redundant information. Differential Revision: https://reviews.llvm.org/D43337 llvm-svn: 326094
* [Hexagon] Recognize non-immediate constants in HexagonConstPropagationKrzysztof Parzyszek2018-02-231-0/+25
| | | | llvm-svn: 325954
* [Hexagon] Return true in enableMultipleCopyHints().Jonas Paulsson2018-02-213-5/+5
| | | | | | | | | | Enable multiple COPY hints to eliminate more COPYs during register allocation. Note that this is something all targets should do, see https://reviews.llvm.org/D38128. Review: Krzysztof Parzyszek llvm-svn: 325697
* [Hexagon] Handle *Low8 register classes in early if-conversionKrzysztof Parzyszek2018-02-201-0/+27
| | | | llvm-svn: 325606
* [Hexagon] Fix alignment calculation of stack objects in Hexagon bit trackerKrzysztof Parzyszek2018-02-201-0/+18
| | | | llvm-svn: 325580
* [Hexagon] Fix lowering of formal arguments after r324737Krzysztof Parzyszek2018-02-151-0/+12
| | | | | | Lowering of formal arguments needs to be aware of vararg functions. llvm-svn: 325255
* [Hexagon] Split HVX vector pair loads/stores, expand unaligned loadsKrzysztof Parzyszek2018-02-142-13/+39
| | | | llvm-svn: 325169
* [DAG] make binops with undef operands consistent with IRSanjay Patel2018-02-121-4/+4
| | | | | | | | | | | | | | | | | | | | | This started by noticing that scalar and vector types were producing different results with div ops in PR36305: https://bugs.llvm.org/show_bug.cgi?id=36305 ...but the problem is bigger. I couldn't keep it straight without a table, so I'm attaching that as a PDF to the review. The x86 tests in undef-ops.ll correspond to that table. Green means that instsimplify and the DAG agree on the result for all types. Red means the DAG was returning undef when IR was not. Yellow means the DAG was returning a non-undef result when IR returned undef. This patch assumes that we're currently doing the right thing in IR. Note: I couldn't find any problems with lowering vector constants as the code comments were warning, but those comments were written long ago in rL36413 . Differential Revision: https://reviews.llvm.org/D43141 llvm-svn: 324941
* [CodeGen] Add a -trap-unreachable option for debuggingDavid Green2018-02-121-1/+1
| | | | | | | | | | | Add a common -trap-unreachable option, similar to the target specific hexagon equivalent, which has been replaced. This turns unreachable instructions into traps, which is useful for debugging. Differential Revision: https://reviews.llvm.org/D42965 llvm-svn: 324880
* [Hexagon] Add code to select QTRUE and QFALSEKrzysztof Parzyszek2018-02-091-0/+29
| | | | | | Fixes http://llvm.org/PR36320. llvm-svn: 324763
* [Hexagon] Express calling conventions via .td file instead of hand-codingKrzysztof Parzyszek2018-02-091-1/+1
| | | | | | Additionally, simplify the rest of the argument/parameter lowering code. llvm-svn: 324737
* [CodeGen] Unify the syntax of MBB liveins in MIR and -debug outputFrancis Visoiu Mistrih2018-02-091-6/+6
| | | | | | | | | | | Instead of: Live Ins: %r0 %r1 print: liveins: %r0, %r1 llvm-svn: 324694
* [CodeGen] Unify the syntax of MBB successors in MIR and -debug outputFrancis Visoiu Mistrih2018-02-091-1/+1
| | | | | | | | | | | Instead of: Successors according to CFG: %bb.6(0x12492492 / 0x80000000 = 14.29%) print: successors: %bb.6(0x12492492); %bb.6(14.29%) llvm-svn: 324685
* [CodeGen] Print MachineBasicBlock labels using MIR syntax in -debug outputFrancis Visoiu Mistrih2018-02-081-1/+1
| | | | | | | | | | | | | | Instead of: %bb.1: derived from LLVM BB %for.body print: bb.1.for.body: Also use MIR syntax for MBB attributes like "align", "landing-pad", etc. llvm-svn: 324563
* [Hexagon] Lower concat of more than 2 vectors into build_vectorKrzysztof Parzyszek2018-02-061-0/+35
| | | | llvm-svn: 324391
* [Hexagon] Don't form new-value jumps from floating-point instructionsKrzysztof Parzyszek2018-02-061-0/+19
| | | | | | | Additionally, verify that the register defined by the producer is a 32-bit register. llvm-svn: 324381
* [Hexagon] Split HVX operations on vector pairsKrzysztof Parzyszek2018-02-063-0/+77
| | | | | | | | Vector pairs are legal types, but not every operation can work on pairs. For those operations that are legal for single vectors, generate a concat of their results on pair halves. llvm-svn: 324350
* [Hexagon] Handle lowering of SETCC via setCondCodeActionKrzysztof Parzyszek2018-02-062-60/+30
| | | | | | | | | | It was expanded directly into instructions earlier. That was to avoid loads from a constant pool for a vector negation: "xor x, splat(i1 -1)". Implement ISD opcodes QTRUE and QFALSE to denote logical vectors of all true and all false values, and handle setcc with negations through selection patterns. llvm-svn: 324348
* [Hexagon] Use V6_vmpyih for halfword multiplicationKrzysztof Parzyszek2018-02-051-4/+2
| | | | | | | Unlike V6_vmpyhv, it produces the result in the exact form that is expected without the need for a shuffle. llvm-svn: 324241
* Followup on Proposal to move MIR physical register namespace to '$' sigil.Puyan Lotfi2018-01-3144-397/+397
| | | | | | | | | | | | Discussed here: http://lists.llvm.org/pipermail/llvm-dev/2018-January/120320.html In preparation for adding support for named vregs we are changing the sigil for physical registers in MIR to '$' from '%'. This will prevent name clashes of named physical register with named vregs. llvm-svn: 323922
* [Hexagon] Implement HVX codegen for vector shiftsKrzysztof Parzyszek2018-01-313-1/+609
| | | | llvm-svn: 323914
* [Hexagon] Handle ANY_EXTEND_VECTOR_INREG in loweringKrzysztof Parzyszek2018-01-311-0/+20
| | | | llvm-svn: 323912
* [Hexagon] Handle SETCC on vector pairs in loweringKrzysztof Parzyszek2018-01-311-0/+29
| | | | llvm-svn: 323911
* [Hexagon] Handle BUILD_VECTOR from undef values in buildHvxVectorRegKrzysztof Parzyszek2018-01-311-0/+39
| | | | llvm-svn: 323889
* [Hexagon] Only process bitcasts of vsplats when selecting const vectorsKrzysztof Parzyszek2018-01-311-0/+37
| | | | | | | | Selecting of constant HVX vectors involves some "manual processing", which mishandled an unrelated BITCAST operation causing a selection error. llvm-svn: 323887
* [RDF] Clear the renamable flag when copy propagating reserved registersKrzysztof Parzyszek2018-01-301-0/+19
| | | | llvm-svn: 323831
* [Hexagon] Handle non-aligned offsets in globals in extender optimizationKrzysztof Parzyszek2018-01-301-0/+34
| | | | | | | | | | Instructions like memd(r0+##global+1) are legal as long as the entire address is properly aligned. Assuming that "global" is aligned at an 8-byte boundary, the expression "global+1" appears to be misaligned. Handle such cases in HexagonConstExtenders, and make sure that any non- extended offsets generated are still aligned accordingly. llvm-svn: 323799
* Revert: [Hexagon] Make sure that offset on globals matches alignment ↵Krzysztof Parzyszek2018-01-301-19/+20
| | | | | | | | | | | | | requirements This reverts r323562, since it wasn't actually necessary. Constant- extended offsets do not need to be aligned, as long as the effective address is aligned. Keep the testcase, with a modification which checks that such offsets are not unnecessarily avoided. llvm-svn: 323798
* [Hexagon] Generate constant splats instead of loads from constant poolKrzysztof Parzyszek2018-01-261-0/+12
| | | | llvm-svn: 323568
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