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* [Hexagon] Check vector elements for equivalence in the ↵Ron Lieberman2017-10-021-0/+86
| | | | | | | | | | | | | HexagonVectorLoopCarriedReuse pass If the two instructions being compared for equivalence have corresponding operands that are integer constants, then check their values to determine equivalence. Patch by Suyog Sarda! llvm-svn: 314642
* [Hexagon] Patch to Extract i1 element from vector of i1Ron Lieberman2017-10-021-0/+9
| | | | | | | This patch extracts 1 element from vector consisting of elements of size 1 bit at given index. llvm-svn: 314641
* Reverted r313993.Galina Kistanova2017-09-271-86/+0
| | | | | | This patch produces a crash and hexagon_vector_loop_carried_reuse_constant.ll test fails on Windows (llvm-clang-x86_64-expensive-checks-win build bot). llvm-svn: 314361
* Check vector elements for equivalence in the HexagonVectorLoopCarriedReuse passPranav Bhandarkar2017-09-221-0/+86
| | | | | | | | | If the two instructions being compared for equivalence have corresponding operands that are integer constants, then check their values to determine equivalence. Patch by Suyog Sarda! llvm-svn: 313993
* [Hexagon] - Fix testcase for the HexagonVectorLoopCarriedReuse pass.Pranav Bhandarkar2017-09-211-0/+86
| | | | llvm-svn: 313936
* Revert "Add a testfile that I missed in a previous commit that added ↵Rafael Espindola2017-09-211-86/+0
| | | | | | | | | | HexagonVectorLoopCarriedReuse pass" This reverts commit r313926. It was failing in some bots. llvm-svn: 313931
* Add a testfile that I missed in a previous commit thatPranav Bhandarkar2017-09-211-0/+86
| | | | | | added HexagonVectorLoopCarriedReuse pass llvm-svn: 313926
* [IfConversion] More simple, correct dead/kill liveness handlingKrzysztof Parzyszek2017-09-144-7/+7
| | | | | | | | Patch by Jesper Antonsson. Differential Revision: https://reviews.llvm.org/D37611 llvm-svn: 313268
* Preserve existing regs when adding pristines to LivePhysRegs/LiveRegUnitsKrzysztof Parzyszek2017-09-081-0/+37
| | | | | | Differential Revision: https://reviews.llvm.org/D37600 llvm-svn: 312797
* Insert IMPLICIT_DEFS for undef uses in tail mergingMatthias Braun2017-09-062-3/+90
| | | | | | | | | | | | | | | | | | | | | Tail merging can convert an undef use into a normal one when creating a common tail. Doing so can make the register live out from a block which previously contained the undef use. To keep the liveness up-to-date, insert IMPLICIT_DEFs in such blocks when necessary. To enable this patch the computeLiveIns() function which used to compute live-ins for a block and set them immediately is split into new functions: - computeLiveIns() just computes the live-ins in a LivePhysRegs set. - addLiveIns() applies the live-ins to a block live-in list. - computeAndAddLiveIns() is a convenience function combining the other two functions and behaving like computeLiveIns() before this patch. Based on a patch by Krzysztof Parzyszek <kparzysz@codeaurora.org> Differential Revision: https://reviews.llvm.org/D37034 llvm-svn: 312668
* [IfConversion] Remove kill flags from common instructions as wellKrzysztof Parzyszek2017-09-061-0/+34
| | | | | | | | | | | | | | | | | | | When if-converting a diamond, two separate blocks will be placed back to back to form a straight line code. To ensure correctness of the liveness information, any registers that are live in the second block should not be killed in the first block, even if they were in the original code. Additionally, when the two blocks share common instructions at the beginning, these instructions will not be duplicated, but only placed once, before both of the blocks. Since the function "isIdenticalTo" (as used here) ignores kill flags, the common initial code in one block may have a kill flag for a register that is live in the other block. Because the code that removes kill flags only runs for the non-common parts of the predicated blocks, a kill flag mismatch in the common code could still lead to a live register being killed prematurely. llvm-svn: 312654
* [Hexagon] Add option to generate calls to "abort" for "unreachable"Krzysztof Parzyszek2017-09-061-0/+8
| | | | llvm-svn: 312644
* [Hexagon] Check for potential bank conflicts in post-RA schedulingKrzysztof Parzyszek2017-08-281-0/+28
| | | | | | | Insert artificial edges between loads that could cause a cache bank conflict. llvm-svn: 311901
* [Hexagon] Generate correct runtime check when recognizing memmoveKrzysztof Parzyszek2017-08-241-0/+45
| | | | | | | | | | | | | | The check (assuming positive stride) for validity of memmove should be (a) the destination is at a lower address than the source, or (b) the distance between the source and destination is greater than or equal the number of bytes copied. For the second part it is sufficient to assume that the destination is at a higher address, since the opposite case is covered by (a). The distance calculation was previously done by subtracting the pointers in the wrong order. llvm-svn: 311650
* [Hexagon] Ignore DBG_VALUEs when counting instructions in hexagon-early-ifKrzysztof Parzyszek2017-08-091-0/+53
| | | | llvm-svn: 310524
* [LSR / TTI / SystemZ] Eliminate TargetTransformInfo::isFoldableMemAccess()Jonas Paulsson2017-08-091-1/+1
| | | | | | | | | | | | | | | | | isLegalAddressingMode() has recently gained the extra optional Instruction* parameter, and therefore it can now do the job that previously only isFoldableMemAccess() could do. The SystemZ implementation of isLegalAddressingMode() has gained the functionality of checking for offsets, which used to be done with isFoldableMemAccess(). The isFoldableMemAccess() hook has been removed everywhere. Review: Quentin Colombet, Ulrich Weigand https://reviews.llvm.org/D35933 llvm-svn: 310463
* [Hexagon] Convert HVX vector constants of i1 to i8Krzysztof Parzyszek2017-08-011-0/+17
| | | | | | | | | Certain operations require vector of i1 values. However, for Hexagon architecture compatibility, they need to be represented as vector of i8. Patch by Suyog Sarda. llvm-svn: 309677
* [Hexagon] Recognize C4_cmpneqi, C4_cmpltei and C4_cmplteui in NewValueJumpKrzysztof Parzyszek2017-07-241-0/+48
| | | | llvm-svn: 308914
* [Hexagon] Add inline-asm constraint 'a' for modifier register classKrzysztof Parzyszek2017-07-211-0/+16
| | | | | | | For example asm ("memw(%0++%1) = %2" : : "r"(addr),"a"(mod),"r"(val) : "memory") llvm-svn: 308761
* [Hexagon] Fix a bug in r308502: post-inc offset is always 0Krzysztof Parzyszek2017-07-191-0/+22
| | | | llvm-svn: 308510
* [Hexagon] Emit lookup tables in text section based on a flagSumanth Gundapaneni2017-07-184-0/+131
| | | | | | | | The flag "-hexagon-emit-lut-text" (defaulted to false) is added to decide on where to keep the switch generated lookup table. Differential Revision: https://reviews.llvm.org/D34818 llvm-svn: 308316
* [llvm] Remove redundant check-prefix=CHECK from tests. NFC.Mandeep Singh Grang2017-07-171-1/+1
| | | | | | | | | | | | Reviewers: t.p.northover, oren_ben_simhon, niravd, mcrosier Reviewed By: oren_ben_simhon, mcrosier Subscribers: nhaehnle, javed.absar, llvm-commits Differential Revision: https://reviews.llvm.org/D35466 llvm-svn: 308193
* [Hexagon] Remove custom lowering of loads of v4i16Krzysztof Parzyszek2017-07-172-0/+23
| | | | | | | The target-independent lowering works fine, except concatenating 32-bit words. Add a pattern to generate A2_combinew instead of 64-bit asl/or. llvm-svn: 308186
* [Hexagon] Add intrinsics for data cache operationsKrzysztof Parzyszek2017-07-141-9/+67
| | | | | | | | | | | | | This is the LLVM part, adding definitions for void @llvm.hexagon.Y2.dccleana(i8*) void @llvm.hexagon.Y2.dccleaninva(i8*) void @llvm.hexagon.Y2.dcinva(i8*) void @llvm.hexagon.Y2.dczeroa(i8*) void @llvm.hexagon.Y4.l2fetch(i8*, i32) void @llvm.hexagon.Y5.l2fetch(i8*, i64) The clang part will follow. llvm-svn: 308032
* [Hexagon] Do not rely on callee-saved info in hasFPKrzysztof Parzyszek2017-07-112-0/+165
| | | | llvm-svn: 307675
* [Hexagon] Add support for nontemporal loads and stores on HVXKrzysztof Parzyszek2017-07-111-0/+28
| | | | | | | | Patch by Michael Wu. Differential Revision: https://reviews.llvm.org/D35104 llvm-svn: 307671
* [Hexagon] Fix check for HMOTF_ConstExtend operand flagKrzysztof Parzyszek2017-07-101-0/+24
| | | | | | This fixes https://llvm.org/PR33718. llvm-svn: 307566
* [Hexagon] Preclude non-memory test from being optimized away. NFC.Nirav Dave2017-07-0511-38/+38
| | | | llvm-svn: 307153
* [Hexagon] Implement frame pointer elimination with -fomit-frame-pointerKrzysztof Parzyszek2017-06-303-24/+92
| | | | | | | It applies to leaf functions that are otherwise not required to have a frame pointer. llvm-svn: 306888
* [Hexagon] Emit jump tables in text section based on a flagSumanth Gundapaneni2017-06-301-0/+57
| | | | | | | | This patch adds a new LLVM flag -hexagon-emit-jt-text which is defaulted to "false". The value "true" emits the switch generated jump tables in text section. Differential Revision: https://reviews.llvm.org/D34820 llvm-svn: 306872
* Revert "[Hexagon] Guard the generation of lookup table"Sumanth Gundapaneni2017-06-301-57/+0
| | | | | | | This reverts commit ae521f4192c3ed0202c047fec993cb59133dd1a0. Wrong commit message llvm-svn: 306871
* [Hexagon] Guard the generation of lookup tableSumanth Gundapaneni2017-06-301-0/+57
| | | | | | | | | The llvm flag "-hexagon-emit-lookup-tables" guards the generation of lookup table from a switch statement. Differential Revision: https://reviews.llvm.org/D34819 llvm-svn: 306869
* [Hexagon] Keep all phi nodes when building DFG in addr-mode-optKrzysztof Parzyszek2017-06-291-0/+30
| | | | | | | The dead phis are needed for finding correct would-be reaching defs in register propagation. llvm-svn: 306690
* Missed a check for UndefVI in r306466Krzysztof Parzyszek2017-06-281-0/+49
| | | | llvm-svn: 306553
* Create a PHI value when merging with a known undef live-inKrzysztof Parzyszek2017-06-271-0/+35
| | | | | | Differential Revision: https://reviews.llvm.org/D34640 llvm-svn: 306466
* [Hexagon] Use proper predicate register state when expanding PS_vselectKrzysztof Parzyszek2017-06-271-0/+53
| | | | llvm-svn: 306458
* [Hexagon] Update kills in hexagon-nvj even more properly than beforeKrzysztof Parzyszek2017-06-271-0/+18
| | | | | | | Account for the fact that both, the feeder and the compare can be moved over instructions that kill registers. llvm-svn: 306443
* [Hexagon] Handle cases when the aligned stack pointer is missingKrzysztof Parzyszek2017-06-262-0/+81
| | | | llvm-svn: 306288
* Revert "[Hexagon] Handle decreasing of stack alignment in frame lowering"Krzysztof Parzyszek2017-06-231-51/+0
| | | | | | This breaks passing of aligned function arguments. llvm-svn: 306145
* [Hexagon] Handle decreasing of stack alignment in frame loweringKrzysztof Parzyszek2017-06-231-0/+51
| | | | llvm-svn: 306124
* [Hexagon] Properly update kill flags in HexagonNewValueJumpKrzysztof Parzyszek2017-06-221-0/+53
| | | | | | | The feeder instruction will be moved to right before the compare, so the updating code should not be looking for kills past the compare. llvm-svn: 306059
* [Hexagon] Use LivePhysRegs to fix up kills in HexagonGenMuxKrzysztof Parzyszek2017-06-223-2/+33
| | | | | | Remove the previous, manual shuffling of the kill flags. llvm-svn: 306054
* [Hexagon] Fix typo in a testcaseKrzysztof Parzyszek2017-06-221-1/+1
| | | | llvm-svn: 306030
* [Hexagon] Handle a global operand to A2_addi when creating duplexesKrzysztof Parzyszek2017-06-221-0/+22
| | | | llvm-svn: 306012
* [Hexagon] Recognize potential offset overflow for store-imm to stackKrzysztof Parzyszek2017-06-221-0/+151
| | | | | | | Reserve an extra scavenging stack slot if the offset field in store- -immediate instructions may overflow. llvm-svn: 306004
* [Hexagon] Handle more types of immediate operands in expand-condsetsKrzysztof Parzyszek2017-06-211-0/+22
| | | | llvm-svn: 305943
* [Hexagon] Don't kill live registers when creating mux out of tfrKrzysztof Parzyszek2017-06-161-0/+17
| | | | | | | | | The second part of r305300: when placing the mux at the later location, make sure that it won't use any register that was killed between the two original instructions. Remove any such kills and transfer them to the mux. llvm-svn: 305553
* [Hexagon] Generate store-immediate instructions for stack objectsKrzysztof Parzyszek2017-06-131-0/+86
| | | | | | | | | Store-immediate instructions have a non-extendable offset. Since the actual offset for a stack object is not known until much later, only generate these stores when the stack size (at the time of instruction selection) is small. llvm-svn: 305305
* [Hexagon] Generate multiply-high instruction in iselKrzysztof Parzyszek2017-06-131-0/+27
| | | | llvm-svn: 305302
* [Hexagon] Don't kill live registers when creating mux out of tfrKrzysztof Parzyszek2017-06-131-0/+15
| | | | | | | | | | | When a mux instruction is created from a pair of complementary conditional transfers, it can be placed at the location of either the earlier or the later of the transfers. Since it will use the operands of the original transfers, putting it in the earlier location may hoist a kill of a source register that was originally further down. Make sure the kill flag is removed if the register is still used afterwards. llvm-svn: 305300
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