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* [Hexagon] Generate instructions for operations on predicate registersKrzysztof Parzyszek2015-07-142-0/+49
| | | | | | | Convert logical operations on general-purpose registers to the correspon- ding operations on predicate registers. llvm-svn: 242186
* [Hexagon] Generate "extract" instructions more aggressivelyKrzysztof Parzyszek2015-07-142-1/+78
| | | | | | | Generate extract instructions (via intrinsics) before the DAG combiner folds shifts into unrecognizable forms. llvm-svn: 242163
* [Hexagon] Add support for atomic RMW operationsKrzysztof Parzyszek2015-07-091-0/+71
| | | | llvm-svn: 241804
* [Hexagon] Implement commoning of GetElementPtr instructionsKrzysztof Parzyszek2015-07-082-0/+113
| | | | llvm-svn: 241714
* [Hexagon] Generate "insert" instructions more aggressivelyKrzysztof Parzyszek2015-07-081-0/+66
| | | | llvm-svn: 241683
* Revert 241681: causes Windows builds to failKrzysztof Parzyszek2015-07-081-66/+0
| | | | llvm-svn: 241682
* [Hexagon] Generate "insert" instructions more aggressivelyKrzysztof Parzyszek2015-07-081-0/+66
| | | | llvm-svn: 241681
* [Hexagon] Printing packet brackets when asm printing and adding a number of ↵Colin LeMahieu2015-06-188-35/+203
| | | | | | tests that test packet brackets. llvm-svn: 240051
* [Hexagon] Adding a number of other tests for min/max instructions and ↵Colin LeMahieu2015-06-1719-2/+327
| | | | | | loading i1s. llvm-svn: 239935
* [Hexagon] Adding some compare tests, fixing existing XFAILed tests, and ↵Colin LeMahieu2015-06-179-8/+331
| | | | | | removing mcpu=hexagonv4 since that's the minimum version anyway. llvm-svn: 239917
* [Hexagon] Adding MC ELF streamer and updating addend relocation test which ↵Colin LeMahieu2015-06-171-1/+1
| | | | | | shows correct ELF symbol. llvm-svn: 239876
* [Hexagon] Using readobj rather than objdump.Colin LeMahieu2015-06-151-1/+1
| | | | llvm-svn: 239770
* [Hexagon] PC-relative offsets are relative to packet start rather than the ↵Colin LeMahieu2015-06-151-0/+10
| | | | | | offset of the relocation. Set relocation addend and check it's correct in the ELF. llvm-svn: 239769
* [Hexagon] Adding some codegen tests and updating some to match spec.Colin LeMahieu2015-06-1312-21/+350
| | | | llvm-svn: 239690
* [Hexagon] Making intrinsic tests agnostic to register allocation. Narrowing ↵Colin LeMahieu2015-06-1211-749/+777
| | | | | | intrinsic parameters to appropriate width. llvm-svn: 239634
* [Hexagon] Adding decoders for signed operands and ensuring all signed ↵Colin LeMahieu2015-06-101-0/+99
| | | | | | operand types disassemble correctly. llvm-svn: 239477
* [Hexagon] Adding functionality for searching for compound instruction pairs. ↵Colin LeMahieu2015-06-081-0/+17
| | | | | | Compound instructions reduce slot resource requirements freeing those packet slots up for more instructions. llvm-svn: 239307
* [Hexagon] Reapply r239097 with tests corrected for shuffling and duplexing.Colin LeMahieu2015-06-055-87/+20
| | | | llvm-svn: 239161
* Shouldn't be XFAIL'ed.Colin LeMahieu2015-06-041-1/+0
| | | | llvm-svn: 239103
* Revert r239095 incorrect test tree.Colin LeMahieu2015-06-042-7/+1
| | | | llvm-svn: 239102
* [Hexagon] Adding functionality for duplexing. Duplexing is a way to ↵Colin LeMahieu2015-06-041-0/+7
| | | | | | compress commonly used pairs of instructions in order to reduce code size. The test case duplex.ll normally would be 8 bytes, assign register to 0 and jump to link register. After duplexing this is only 4 bytes. This also tests the HexagonMCShuffler code path which is used to make sure duplexed instructions still follow slot requirements. llvm-svn: 239095
* [Hexagon] Test doesn't work on all platforms. At any rate the uninitialized ↵Colin LeMahieu2015-06-031-7/+0
| | | | | | variable issue was fixed. Removing re-registering ASM backend. llvm-svn: 238949
* [Hexagon] Reapply 238772 OSABI was not correctly set, added empty_elf test ↵Colin LeMahieu2015-06-032-0/+21
| | | | | | to make sure it is. llvm-svn: 238947
* Revert "[Hexagon] Adding basic ELF relocation generation and testing ↵Rafael Espindola2015-06-011-14/+0
| | | | | | | | | | | | advanced relaxation codepath." This reverts commit r238748. It broke the msan bot: http://lab.llvm.org:8011/builders/sanitizer-x86_64-linux-fast/builds/4372/steps/check-llvm%20msan/logs/stdio llvm-svn: 238772
* [Hexagon] Adding basic ELF relocation generation and testing advanced ↵Colin LeMahieu2015-06-011-0/+14
| | | | | | relaxation codepath. llvm-svn: 238748
* [Hexagon] Disassembling, printing, and emitting instructions a whole-bundle ↵Colin LeMahieu2015-05-292-0/+2
| | | | | | at a time which is the semantic unit for Hexagon. Fixing tests to use the new format. Disabling tests in the direct object emission path for a followup patch. llvm-svn: 238556
* [Hexagon] Generate hardware loop for a vectorized loopBrendon Cahoon2015-05-141-0/+93
| | | | | | | | | The induction variable in the vectorized loop wasn't recognized properly, so a hardware loop wasn't generated. Differential Revision: http://reviews.llvm.org/D9722 llvm-svn: 237388
* [Hexagon] Remove dead constant assignment in hardware loop passBrendon Cahoon2015-05-141-0/+23
| | | | | | | | | | | After converting a loop to a hardware loop, the pass should remove any unnecessary instructions from the old compare-and-branch code. This patch removes a dead constant assignment that was used in the compare instruction. Differential Revision: http://reviews.llvm.org/D9720 llvm-svn: 237373
* [Hexagon] Check for underflow/wrap in hardware loop passBrendon Cahoon2015-05-144-0/+198
| | | | | | | | If the loop trip count may underflow or wrap, the compiler should not generate a hardware loop since the trip count will be incorrect. llvm-svn: 237365
* [Hexagon] Generate loop1 instruction for nested loopsBrendon Cahoon2015-05-131-0/+68
| | | | | | | | loop1 is for the outer loop and loop0 is for the inner loop. Differential Revision: http://reviews.llvm.org/D9680 llvm-svn: 237266
* [Hexagon] Generate hardware loop when loop has a critical edgeBrendon Cahoon2015-05-131-0/+58
| | | | | | | | | The hardware loop pass should try to generate a hardware loop instruction when the original loop has a critical edge. Differential Revision: http://reviews.llvm.org/D9678 llvm-svn: 237258
* [PATCH] [HEXAGON] Add a test program to verify calling conventionSundeep Kushwaha2015-05-121-0/+13
| | | | | | | | for large struct return by value. Differential Revision: http://reviews.llvm.org/D9709 llvm-svn: 237170
* [Hexagon] Generate more hardware loopsBrendon Cahoon2015-05-087-89/+450
| | | | | | | | | Refactored parts of the hardware loop pass to generate more. Also, added more tests. Differential Revision: http://reviews.llvm.org/D9568 llvm-svn: 236896
* [Hexagon] Update AnalyzeBranch, etc target hooksBrendon Cahoon2015-05-082-0/+655
| | | | | | | | | | | | | Improved the AnalyzeBranch, InsertBranch, and RemoveBranch functions in order to handle more of our branch instructions. This requires changes to analyzeCompare and PredicateInstructions. Specifically, we've added support for new value compare jumps, improved handling of endloop, added more compare instructions, and improved support for predicate instructions. Differential Revision: http://reviews.llvm.org/D9559 llvm-svn: 236876
* IR: Give 'DI' prefix to debug info metadataDuncan P. N. Exon Smith2015-04-291-24/+24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Finish off PR23080 by renaming the debug info IR constructs from `MD*` to `DI*`. The last of the `DIDescriptor` classes were deleted in r235356, and the last of the related typedefs removed in r235413, so this has all baked for about a week. Note: If you have out-of-tree code (like a frontend), I recommend that you get everything compiling and tests passing with the *previous* commit before updating to this one. It'll be easier to keep track of what code is using the `DIDescriptor` hierarchy and what you've already updated, and I think you're extremely unlikely to insert bugs. YMMV of course. Back to *this* commit: I did this using the rename-md-di-nodes.sh upgrade script I've attached to PR23080 (both code and testcases) and filtered through clang-format-diff.py. I edited the tests for test/Assembler/invalid-generic-debug-node-*.ll by hand since the columns were off-by-three. It should work on your out-of-tree testcases (and code, if you've followed the advice in the previous paragraph). Some of the tests are in badly named files now (e.g., test/Assembler/invalid-mdcompositetype-missing-tag.ll should be 'dicompositetype'); I'll come back and move the files in a follow-up commit. llvm-svn: 236120
* [Hexagon] Use constant extenders to fix up hardware loopsBrendon Cahoon2015-04-271-0/+36
| | | | | | | | | | Use a loop instruction with a constant extender for a hardware loop instruction that is too far away from the start of the loop. This is cheaper than changing the SA register value. Differential Revision: http://reviews.llvm.org/D9262 llvm-svn: 235882
* [PATCH] [Hexagon] Adding a test case for calling convention.Sundeep Kushwaha2015-04-241-0/+73
| | | | | | http://reviews.llvm.org/D9241 llvm-svn: 235754
* [Hexagon] Shrink-wrap stack frame (Hexagon-specific)Krzysztof Parzyszek2015-04-231-0/+36
| | | | llvm-svn: 235603
* [Hexagon] Add testcases for stack alignment and variable-sized objectsKrzysztof Parzyszek2015-04-234-0/+89
| | | | llvm-svn: 235602
* [Hexagon] Some cleanup of instruction selection codeKrzysztof Parzyszek2015-04-226-16/+17
| | | | llvm-svn: 235552
* [Hexagon] Use A2_tfrsi for constant pool and jump table addressesKrzysztof Parzyszek2015-04-222-3/+4
| | | | llvm-svn: 235535
* [Hexagon] Patterns for frame index with offset for iselKrzysztof Parzyszek2015-04-211-0/+29
| | | | llvm-svn: 235418
* [opaque pointer type] Add textual IR support for explicit type parameter to ↵David Blaikie2015-04-163-8/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | the call instruction See r230786 and r230794 for similar changes to gep and load respectively. Call is a bit different because it often doesn't have a single explicit type - usually the type is deduced from the arguments, and just the return type is explicit. In those cases there's no need to change the IR. When that's not the case, the IR usually contains the pointer type of the first operand - but since typed pointers are going away, that representation is insufficient so I'm just stripping the "pointerness" of the explicit type away. This does make the IR a bit weird - it /sort of/ reads like the type of the first operand: "call void () %x(" but %x is actually of type "void ()*" and will eventually be just of type "ptr". But this seems not too bad and I don't think it would benefit from repeating the type ("void (), void () * %x(" and then eventually "void (), ptr %x(") as has been done with gep and load. This also has a side benefit: since the explicit type is no longer a pointer, there's no ambiguity between an explicit type and a function that returns a function pointer. Previously this case needed an explicit type (eg: a function returning a void() function was written as "call void () () * @x(" rather than "call void () * @x(" because of the ambiguity between a function returning a pointer to a void() function and a function returning void). No ambiguity means even function pointer return types can just be written alone, without writing the whole function's type. This leaves /only/ the varargs case where the explicit type is required. Given the special type syntax in call instructions, the regex-fu used for migration was a bit more involved in its own unique way (as every one of these is) so here it is. Use it in conjunction with the apply.sh script and associated find/xargs commands I've provided in rr230786 to migrate your out of tree tests. Do let me know if any of this doesn't cover your cases & we can iterate on a more general script/regexes to help others with out of tree tests. About 9 test cases couldn't be automatically migrated - half of those were functions returning function pointers, where I just had to manually delete the function argument types now that we didn't need an explicit function type there. The other half were typedefs of function types used in calls - just had to manually drop the * from those. import fileinput import sys import re pat = re.compile(r'((?:=|:|^|\s)call\s(?:[^@]*?))(\s*$|\s*(?:(?:\[\[[a-zA-Z0-9_]+\]\]|[@%](?:(")?[\\\?@a-zA-Z0-9_.]*?(?(3)"|)|{{.*}}))(?:\(|$)|undef|inttoptr|bitcast|null|asm).*$)') addrspace_end = re.compile(r"addrspace\(\d+\)\s*\*$") func_end = re.compile("(?:void.*|\)\s*)\*$") def conv(match, line): if not match or re.search(addrspace_end, match.group(1)) or not re.search(func_end, match.group(1)): return line return line[:match.start()] + match.group(1)[:match.group(1).rfind('*')].rstrip() + match.group(2) + line[match.end():] for line in sys.stdin: sys.stdout.write(conv(re.search(pat, line), line)) llvm-svn: 235145
* Revert revisions r234755, r234759, r234760Jan Vesely2015-04-132-5/+15
| | | | | | | | | | | Revert "Remove default in fully-covered switch (to fix Clang -Werror -Wcovered-switch-default)" Revert "R600: Add carry and borrow instructions. Use them to implement UADDO/USUBO" Revert "LegalizeDAG: Try to use Overflow operations when expanding ADD/SUB" Using overflow operations fails CodeGen/Generic/2011-07-07-ScheduleDAGCrash.ll on hexagon, nvptx, and r600. Revert while I investigate. llvm-svn: 234768
* Allow memory intrinsics to be tail callsKrzysztof Parzyszek2015-04-131-0/+31
| | | | llvm-svn: 234764
* LegalizeDAG: Try to use Overflow operations when expanding ADD/SUBJan Vesely2015-04-132-15/+5
| | | | | | | | | | v2: consider BooleanContents when processing overflow Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu> Reviewers: resistor, jholewinsky (nvidia parts) Differential Revision: http://reviews.llvm.org/D6340 llvm-svn: 234755
* Expand MUX instructions early on HexagonKrzysztof Parzyszek2015-03-315-2/+172
| | | | | | This time with all files included. llvm-svn: 233696
* Revert 233694. Weak SVN-fu.Krzysztof Parzyszek2015-03-312-2/+2
| | | | llvm-svn: 233695
* Expand MUX instructions early on HexagonKrzysztof Parzyszek2015-03-312-2/+2
| | | | llvm-svn: 233694
* [Hexagon] Add support for vector instructionsKrzysztof Parzyszek2015-03-1944-0/+1513
| | | | llvm-svn: 232728
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