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* Move .mir tests to appropriate directoriesMatthias Braun2016-12-091-0/+34
| | | | | | | | | | | test/CodeGen/MIR should contain tests that intent to test the MIR printing or parsing. Tests that test something else should be in test/CodeGen/TargetName even when they are written in .mir. As a rule of thumb, only tests using "llc -run-pass none" should be in test/CodeGen/MIR. llvm-svn: 289254
* [Hexagon] Remove unsafe load instructions that affect Stack Slot ColoringSumanth Gundapaneni2016-11-141-0/+131
| | | | | | | | | | | | | | | | | The Stack slot coloring pass removes a store that is followed by a load that deal with the same stack slot. The function isLoadFromStackSlot is supposed to consider the loads that have no side-effects. This patch fixed the issue by removing the unsafe loads from this function Eg: %vreg0<def> = L2_loadruh_io <fi#15>, 0 S2_storeri_io <fi#15>, 0, %vreg0 In this case, we load an unsigned extended half word and store this in to the same stack slot. The Stack slot coloring pass considers safe to remove the store. This patch marked all the non-vector byte and half word loads as unsafe. llvm-svn: 286843
* [Hexagon] Separate Hexagon subreg indices for different register classesKrzysztof Parzyszek2016-11-092-14/+14
| | | | | | | | | | | For pairs of 32-bit registers: isub_lo, isub_hi. For pairs of vector registers: vsub_lo, vsub_hi. Add generic subreg indices: ps_sub_lo, ps_sub_hi, and a function HexagonRegisterInfo::getHexagonSubRegIndex(RegClass, GenericSubreg) that returns the appropriate subreg index for RegClass. llvm-svn: 286377
* [Hexagon] Eliminate Insert4 pseudo-instruction, use combines insteadKrzysztof Parzyszek2016-11-091-5/+5
| | | | llvm-svn: 286368
* [Hexagon] Account for <def,read-undef> when validating moves for predicationKrzysztof Parzyszek2016-11-041-0/+41
| | | | llvm-svn: 286009
* [Hexagon] Remove registers coalesced in expand-condsets from live intervalsKrzysztof Parzyszek2016-11-021-0/+49
| | | | llvm-svn: 285846
* [Hexagon] Don't expand mux instructions with both sources identicalKrzysztof Parzyszek2016-10-311-0/+32
| | | | llvm-svn: 285588
* Handle non-~0 lane masks on live-in registers in LivePhysRegsKrzysztof Parzyszek2016-10-281-0/+55
| | | | | | | | | | | | | | | | | When LivePhysRegs adds live-in registers, it recognizes ~0 as a special lane mask indicating the entire register. If the lane mask is not ~0, it will only add the subregisters that overlap the specified lane mask. The problem is that if a live-in register does not have subregisters, and the lane mask is not ~0, it will not be added to the live set. (The given lane mask may simply be the lane mask of its register class.) If a register does not have subregisters, add it to the live set if the lane mask is non-zero. Differential Revision: https://reviews.llvm.org/D26094 llvm-svn: 285440
* [Hexagon] Maintain kill flags through splitting in expand-condsetsKrzysztof Parzyszek2016-10-281-0/+78
| | | | | | | Do not use LiveIntervals to recalculate kills, because that cannot be done accurately without implicit uses on predicated instructions. llvm-svn: 285409
* [Hexagon] Do not expand ISD::SELECT for HVX vectorsKrzysztof Parzyszek2016-10-271-0/+69
| | | | llvm-svn: 285297
* [Hexagon] Handle spills of partially defined double vector registersKrzysztof Parzyszek2016-10-211-0/+95
| | | | | | | | | | | | After register allocation it is possible to have a spill of a register that is only partially defined. That in itself it fine, but creates a problem for double vector registers. Stores of such registers are pseudo instructions that are expanded into pairs of individual vector stores, and in case of a partially defined source, one of the stores may use an entirely undefined register. To avoid this, track the defined parts and only generate actual stores for those. llvm-svn: 284841
* [RDF] Switch RefMap in liveness calculation to use lane masksKrzysztof Parzyszek2016-10-191-0/+60
| | | | | | | | | | This required reengineering of some of the part of liveness calculation, including fixing some issues caused by the limitations of the previous approach. The current code is not necessarily the fastest, but it should be functionally correct (at least more so than before). The compile-time performance will be addressed in the future. llvm-svn: 284609
* Handle lane masks in LivePhysRegs when adding live-insKrzysztof Parzyszek2016-10-121-0/+40
| | | | | | Differential Revision: https://reviews.llvm.org/D25533 llvm-svn: 284076
* Do not remove implicit defs in BranchFolderKrzysztof Parzyszek2016-10-121-0/+29
| | | | | | | | | | | Branch folder removes implicit defs if they are the only non-branching instructions in a block, and the branches do not use the defined registers. The problem is that in some cases these implicit defs are required for the liveness information to be correct. Differential Revision: https://reviews.llvm.org/D25478 llvm-svn: 284036
* [Hexagon] Avoid replacing full regs with subregisters in tied operandsKrzysztof Parzyszek2016-10-061-0/+23
| | | | | | Doing so will result in the two-address pass generating incorrect code. llvm-svn: 283463
* [RDF] Fix live def propagation through basic blockKrzysztof Parzyszek2016-10-051-0/+214
| | | | llvm-svn: 283371
* Fix machine operand traversal in ScheduleDAGInstrs::fixupKillsKrzysztof Parzyszek2016-10-051-0/+37
| | | | llvm-svn: 283315
* Set some tests to an unknown vendor and OSMatthias Braun2016-10-033-3/+3
| | | | | | | | This avoids llc using the hosts OS/vendor as defaults and triggering unwanted behaviour in the tests. This should deal with the buildbot breakages on windows after r283140. llvm-svn: 283149
* [RDF] Fix liveness propagation through shadowsKrzysztof Parzyszek2016-10-031-0/+73
| | | | | | | | Each shadow only represents data flow that is restricted to its reaching def. Propagating more than that could lead to spurious register liveness, resulting in extra (incorrectly) block live-ins. llvm-svn: 283143
* IfConversion: Add implicit uses for redefined regs with live subregistersKrzysztof Parzyszek2016-09-281-0/+50
| | | | | | | | | | Normally, if conversion would add implicit uses for redefined registers, e.g. R0<def> = add_if ..., R0<imp-use>. However, if only subregisters of R0 are known to be live but not R0 itself, such implicit uses will not be added, causing prior definitions of such subregisters and R0 itself to become dead. llvm-svn: 282626
* [Hexagon] segv while processing SUnit with nullNodePtrRon Lieberman2016-09-171-0/+202
| | | | | | Added BoundaryNode check to isBestZeroLatency function. llvm-svn: 281825
* This reapplies r281304. The issue was that I had missedSjoerd Meijer2016-09-141-25/+5
| | | | | | to copy the new isAdd field in the tablegen data structure. llvm-svn: 281447
* [Hexagon] Better handling of HVX vector loweringKrzysztof Parzyszek2016-09-131-0/+21
| | | | | | | - Expand SELECT_CC and BR_CC for vector types. - Implement TLI::isShuffleMaskLegal. llvm-svn: 281397
* [Hexagon] Clear the flow queue after visiting a single instructionKrzysztof Parzyszek2016-09-131-0/+47
| | | | llvm-svn: 281339
* Revert of r281304 as it is causing build bot failures in hexagonSjoerd Meijer2016-09-131-5/+25
| | | | | | | hwloop regression tests. These tests pass locally; will be investigating where these differences come from. llvm-svn: 281306
* This adds a new field isAdd to MCInstrDesc. The ARM and Hexagon instructionSjoerd Meijer2016-09-131-25/+5
| | | | | | | | | | | descriptions now tag add instructions, and the Hexagon backend is using this to identify loop induction statements. Patch by Sam Parker and Sjoerd Meijer. Differential Revision: https://reviews.llvm.org/D23601 llvm-svn: 281304
* [RDF] Further improve handling of multiple phis reached from shadowsKrzysztof Parzyszek2016-09-081-0/+40
| | | | llvm-svn: 280987
* [Hexagon] Expand sext- and zextloads of vector types, not just extloadsKrzysztof Parzyszek2016-09-081-0/+10
| | | | | | Recent change exposed this issue, breaking the Hexagon buildbots. llvm-svn: 280973
* [RDF] Fix liveness analysis for phi nodes with shadow usesKrzysztof Parzyszek2016-09-071-0/+64
| | | | | | | | Shadow uses need to be analyzed together, since each individual shadow will only have a partial reaching def. All shadows together may cover a given register ref, while each individual shadow may not. llvm-svn: 280855
* [RDF] Ignore undef use operandsKrzysztof Parzyszek2016-09-061-0/+55
| | | | llvm-svn: 280717
* [Hexagon] Deal with undefs when extending live intervalsKrzysztof Parzyszek2016-09-011-0/+112
| | | | | | Reapply r280275, since MSVC accepts r280358. llvm-svn: 280369
* Revert "Add an optional parameter with a list of undefs to extendToIndices"Reid Kleckner2016-08-311-112/+0
| | | | | | | | | | | | This reverts commit r280268, it causes all MSVC 2013 to ICE. This appears to have been fixed in a later MSVC 2013 update, because I cannot reproduce it locally. That said, all upstream LLVM bots are broken right now, so I am reverting. Also reverts dependent change r280275, "[Hexagon] Deal with undefs when extending live intervals". llvm-svn: 280301
* [Hexagon] Deal with undefs when extending live intervalsKrzysztof Parzyszek2016-08-311-0/+112
| | | | llvm-svn: 280275
* Fixed spill stack objects are mutableKrzysztof Parzyszek2016-08-311-0/+69
| | | | | | Differential Revision: https://reviews.llvm.org/D24039 llvm-svn: 280244
* Propagate TBAA info in SelectionDAG::getIndexedLoadKrzysztof Parzyszek2016-08-291-0/+37
| | | | | | Patch by Pranav Bhandarkar. llvm-svn: 279998
* IfConversion: Fix branch predication bug.Kyle Butt2016-08-291-0/+37
| | | | | | | | | | | | This bug shows up with diamonds that share unpredicable, unanalyzable branches. There's an included test case from Hexagon. What was happening was that we were attempting to predicate the branch instruction despite the fact that it was checked to be the same. Now for unanalyzable branches we skip over the branch instructions when predicating the block. Differential Revision: https://reviews.llvm.org/D23939 llvm-svn: 279985
* [Hexagon] vector store print tracing.Ron Lieberman2016-08-251-0/+5
| | | | | | | | Add vector store print tracing option for hexagon vector instructions. https://reviews.llvm.org/D23870 llvm-svn: 279739
* MachineFunctionProperties/MIRParser: Rename AllVRegsAllocated->NoVRegs, ↵Matthias Braun2016-08-251-1/+0
| | | | | | | | | | | | | compute it Rename AllVRegsAllocated to NoVRegs. This avoids the connotation of running after register and simply describes that no vregs are used in a machine function. With that we can simply compute the property and do not need to dump/parse it in .mir files. Differential Revision: http://reviews.llvm.org/D23850 llvm-svn: 279698
* [Hexagon] Check for block end when skipping debug instructionsKrzysztof Parzyszek2016-08-241-0/+57
| | | | llvm-svn: 279681
* Missed a test in my last commitMatthias Braun2016-08-241-1/+0
| | | | llvm-svn: 279679
* Create subranges for new intervals resulting from live interval splittingKrzysztof Parzyszek2016-08-241-0/+205
| | | | | | | | | | | | | | | | | | | The register allocator can split a live interval of a register into a set of smaller intervals. After the allocation of registers is complete, the rewriter will modify the IR to replace virtual registers with the corres- ponding physical registers. At this stage, if a register corresponding to a subregister of a virtual register is used, the rewriter will check if that subregister is undefined, and if so, it will add the <undef> flag to the machine operand. The function verifying liveness of the subregis- ter would assume that it is undefined, unless any of the subranges of the live interval proves otherwise. The problem is that the live intervals created during splitting do not have any subranges, even if the original parent interval did. This could result in the <undef> flag placed on a register that is actually defined. Differential Revision: http://reviews.llvm.org/D21189 llvm-svn: 279625
* [Hexagon] Packetize return value setup with the return instructionKrzysztof Parzyszek2016-08-231-0/+37
| | | | | | Commit r279241 unintentionally reverted that ability. llvm-svn: 279526
* [Hexagon] Add RUN line to testKrzysztof Parzyszek2016-08-191-0/+4
| | | | llvm-svn: 279304
* [Hexagon] Allow i1 values for 'r' constraint in inline-asmKrzysztof Parzyszek2016-08-191-0/+10
| | | | llvm-svn: 279302
* [Hexagon] Fixes for new-value jump formationKrzysztof Parzyszek2016-08-191-0/+63
| | | | | | | - Recognize C2_cmpgtui, S2_tstbit_i, and S4_ntstbit_i. - Avoid creating new-value instructions with both source operands equal. llvm-svn: 279286
* [Hexagon] Enforce LLSC packetization rulesKrzysztof Parzyszek2016-08-191-0/+12
| | | | | | | | | Ensure that load locked and store conditional instructions are only packetized with ALU32 instructions. Patch by Ben Craig. llvm-svn: 279272
* [Hexagon] Fix incorrect generation of S4_subi_asl_riKrzysztof Parzyszek2016-08-191-0/+70
| | | | | | Patch by Jyotsna Verma. llvm-svn: 279267
* [Hexagon] Allow tail-call optimization when mixing C and fast calling convKrzysztof Parzyszek2016-08-191-0/+22
| | | | | | Patch by Arnold Schwaighofer. llvm-svn: 279251
* [Hexagon] Check for empty live intervalKrzysztof Parzyszek2016-08-191-0/+47
| | | | | | Patch by Brendon Cahoon. llvm-svn: 279249
* [Hexagon] Mark PS_jumpret as pseudo-instruction, expand it into J2_jumprKrzysztof Parzyszek2016-08-191-4/+3
| | | | llvm-svn: 279241
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