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* Let SelectionDAG start to use probability-based interface to add successors.Cong Hou2015-11-241-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | The patch in http://reviews.llvm.org/D13745 is broken into four parts: 1. New interfaces without functional changes. 2. Use new interfaces in SelectionDAG, while in other passes treat probabilities as weights. 3. Use new interfaces in all other passes. 4. Remove old interfaces. This the second patch above. In this patch SelectionDAG starts to use probability-based interfaces in MBB to add successors but other MC passes are still using weight-based interfaces. Therefore, we need to maintain correct weight list in MBB even when probability-based interfaces are used. This is done by updating weight list in probability-based interfaces by treating the numerator of probabilities as weights. This change affects many test cases that check successor weight values. I will update those test cases once this patch looks good to you. Differential revision: http://reviews.llvm.org/D14361 llvm-svn: 253965
* Revert "Change memcpy/memset/memmove to have dest and source alignments."Pete Cooper2015-11-192-8/+8
| | | | | | | | | | This reverts commit r253511. This likely broke the bots in http://lab.llvm.org:8011/builders/clang-ppc64-elf-linux2/builds/20202 http://bb.pgr.jp/builders/clang-3stage-i686-linux/builds/3787 llvm-svn: 253543
* Change memcpy/memset/memmove to have dest and source alignments.Pete Cooper2015-11-182-8/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Note, this was reviewed (and more details are in) http://lists.llvm.org/pipermail/llvm-commits/Week-of-Mon-20151109/312083.html These intrinsics currently have an explicit alignment argument which is required to be a constant integer. It represents the alignment of the source and dest, and so must be the minimum of those. This change allows source and dest to each have their own alignments by using the alignment attribute on their arguments. The alignment argument itself is removed. There are a few places in the code for which the code needs to be checked by an expert as to whether using only src/dest alignment is safe. For those places, they currently take the minimum of src/dest alignments which matches the current behaviour. For example, code which used to read: call void @llvm.memcpy.p0i8.p0i8.i32(i8* %dest, i8* %src, i32 500, i32 8, i1 false) will now read: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 8 %dest, i8* align 8 %src, i32 500, i1 false) For out of tree owners, I was able to strip alignment from calls using sed by replacing: (call.*llvm\.memset.*)i32\ [0-9]*\,\ i1 false\) with: $1i1 false) and similarly for memmove and memcpy. I then added back in alignment to test cases which needed it. A similar commit will be made to clang which actually has many differences in alignment as now IRBuilder can generate different source/dest alignments on calls. In IRBuilder itself, a new argument was added. Instead of calling: CreateMemCpy(Dst, Src, getInt64(Size), DstAlign, /* isVolatile */ false) you now call CreateMemCpy(Dst, Src, getInt64(Size), DstAlign, SrcAlign, /* isVolatile */ false) There is a temporary class (IntegerAlignment) which takes the source alignment and rejects implicit conversion from bool. This is to prevent isVolatile here from passing its default parameter to the source alignment. Note, changes in future can now be made to codegen. I didn't change anything here, but this change should enable better memcpy code sequences. Reviewed by Hal Finkel. llvm-svn: 253511
* [Hexagon] Fixing compound register printing and reenabling more tests.Colin LeMahieu2015-11-101-1/+0
| | | | llvm-svn: 252574
* [Hexagon] Fixing store instructions and reenabling a few more tests.Colin LeMahieu2015-11-102-2/+0
| | | | llvm-svn: 252561
* [Hexagon] Fixing load instruction parsing and reenabling tests.Colin LeMahieu2015-11-102-2/+0
| | | | llvm-svn: 252555
* [Hexagon] Enabling ASM parsing on Hexagon backend and adding instruction ↵Colin LeMahieu2015-11-096-0/+6
| | | | | | parsing tests. General updating of the code emission. llvm-svn: 252443
* DI: Reverse direction of subprogram -> function edge.Peter Collingbourne2015-11-052-4/+4
| | | | | | | | | | | | | | | | | | | | | | | Previously, subprograms contained a metadata reference to the function they described. Because most clients need to get or set a subprogram for a given function rather than the other way around, this created unneeded inefficiency. For example, many passes needed to call the function llvm::makeSubprogramMap() to build a mapping from functions to subprograms, and the IR linker needed to fix up function references in a way that caused quadratic complexity in the IR linking phase of LTO. This change reverses the direction of the edge by storing the subprogram as function-level metadata and removing DISubprogram's function field. Since this is an IR change, a bitcode upgrade has been provided. Fixes PR23367. An upgrade script for textual IR for out-of-tree clients is attached to the PR. Differential Revision: http://reviews.llvm.org/D14265 llvm-svn: 252219
* Tail duplication can mix incompatible registers in phi nodesKrzysztof Parzyszek2015-10-211-0/+28
| | | | | | | | | Do not tail duplicate blocks where the successor has a phi node, and the corresponding value in that phi node uses a subregister. http://reviews.llvm.org/D13922 llvm-svn: 250877
* [Hexagon] Bit-based instruction simplificationKrzysztof Parzyszek2015-10-206-4/+137
| | | | | | | Analyze bit patterns of operands and values of instructions to perform various simplifications, dead/redundant code elimination, etc. llvm-svn: 250868
* [Hexagon] Delay emission of CFI instructionsKrzysztof Parzyszek2015-10-193-6/+70
| | | | | | | Emit the CFI instructions after all code transformation have been done. This will avoid any interference between CFI instructions and packetization. llvm-svn: 250714
* [Hexagon] Split double registersKrzysztof Parzyszek2015-10-1616-93/+118
| | | | llvm-svn: 250549
* [Hexagon] Merge adjacent storesKrzysztof Parzyszek2015-10-164-0/+69
| | | | llvm-svn: 250542
* [Hexagon] Add an early if-conversion passKrzysztof Parzyszek2015-10-065-1/+562
| | | | llvm-svn: 249423
* Update edge weights properly when merging blocks in if-conversion.Cong Hou2015-09-181-0/+64
| | | | | | | | In if-conversion, there is a utility function MergeBlocks() that is used to merge blocks. However, when new edges are built in this function the edge weight is either not provided or not updated properly, leading to a modified CFG with incorrect edge weights. This patch corrects this issue. Differential Revision: http://reviews.llvm.org/D12513 llvm-svn: 248030
* DI: Require subprogram definitions to be distinctDuncan P. N. Exon Smith2015-08-281-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | As a follow-up to r246098, require `DISubprogram` definitions (`isDefinition: true`) to be 'distinct'. Specifically, add an assembler check, a verifier check, and bitcode upgrading logic to combat testcase bitrot after the `DIBuilder` change. While working on the testcases, I realized that test/Linker/subprogram-linkonce-weak-odr.ll isn't relevant anymore. Its purpose was to check for a corner case in PR22792 where two subprogram definitions match exactly and share the same metadata node. The new verifier check, requiring that subprogram definitions are 'distinct', precludes that possibility. I updated almost all the IR with the following script: git grep -l -E -e '= !DISubprogram\(.* isDefinition: true' | grep -v test/Bitcode | xargs sed -i '' -e 's/= \(!DISubprogram(.*, isDefinition: true\)/= distinct \1/' Likely some variant of would work for out-of-tree testcases. llvm-svn: 246327
* DI: Disallow uniquable DICompileUnitsDuncan P. N. Exon Smith2015-08-031-1/+1
| | | | | | | | | | | | | | | | | | Since r241097, `DIBuilder` has only created distinct `DICompileUnit`s. The backend is liable to start relying on that (if it hasn't already), so make uniquable `DICompileUnit`s illegal and automatically upgrade old bitcode. This is a nice cleanup, since we can remove an unnecessary `DenseSet` (and the associated uniquing info) from `LLVMContextImpl`. Almost all the testcases were updated with this script: git grep -e '= !DICompileUnit' -l -- test | grep -v test/Bitcode | xargs sed -i '' -e 's,= !DICompileUnit,= distinct !DICompileUnit,' I imagine something similar should work for out-of-tree testcases. llvm-svn: 243885
* DI: Remove DW_TAG_arg_variable and DW_TAG_auto_variableDuncan P. N. Exon Smith2015-07-311-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | Remove the fake `DW_TAG_auto_variable` and `DW_TAG_arg_variable` tags, using `DW_TAG_variable` in their place Stop exposing the `tag:` field at all in the assembly format for `DILocalVariable`. Most of the testcase updates were generated by the following sed script: find test/ -name "*.ll" -o -name "*.mir" | xargs grep -l 'DILocalVariable' | xargs sed -i '' \ -e 's/tag: DW_TAG_arg_variable, //' \ -e 's/tag: DW_TAG_auto_variable, //' There were only a handful of tests in `test/Assembly` that I needed to update by hand. (Note: a follow-up could change `DILocalVariable::DILocalVariable()` to set the tag to `DW_TAG_formal_parameter` instead of `DW_TAG_variable` (as appropriate), instead of having that logic magically in the backend in `DbgVariable`. I've added a FIXME to that effect.) llvm-svn: 243774
* [Hexagon] Generate MUX from conditional transfers when dot-new not possibleKrzysztof Parzyszek2015-07-201-0/+28
| | | | llvm-svn: 242711
* [Hexagon] Generate instructions for operations on predicate registersKrzysztof Parzyszek2015-07-142-0/+49
| | | | | | | Convert logical operations on general-purpose registers to the correspon- ding operations on predicate registers. llvm-svn: 242186
* [Hexagon] Generate "extract" instructions more aggressivelyKrzysztof Parzyszek2015-07-142-1/+78
| | | | | | | Generate extract instructions (via intrinsics) before the DAG combiner folds shifts into unrecognizable forms. llvm-svn: 242163
* [Hexagon] Add support for atomic RMW operationsKrzysztof Parzyszek2015-07-091-0/+71
| | | | llvm-svn: 241804
* [Hexagon] Implement commoning of GetElementPtr instructionsKrzysztof Parzyszek2015-07-082-0/+113
| | | | llvm-svn: 241714
* [Hexagon] Generate "insert" instructions more aggressivelyKrzysztof Parzyszek2015-07-081-0/+66
| | | | llvm-svn: 241683
* Revert 241681: causes Windows builds to failKrzysztof Parzyszek2015-07-081-66/+0
| | | | llvm-svn: 241682
* [Hexagon] Generate "insert" instructions more aggressivelyKrzysztof Parzyszek2015-07-081-0/+66
| | | | llvm-svn: 241681
* [Hexagon] Printing packet brackets when asm printing and adding a number of ↵Colin LeMahieu2015-06-188-35/+203
| | | | | | tests that test packet brackets. llvm-svn: 240051
* [Hexagon] Adding a number of other tests for min/max instructions and ↵Colin LeMahieu2015-06-1719-2/+327
| | | | | | loading i1s. llvm-svn: 239935
* [Hexagon] Adding some compare tests, fixing existing XFAILed tests, and ↵Colin LeMahieu2015-06-179-8/+331
| | | | | | removing mcpu=hexagonv4 since that's the minimum version anyway. llvm-svn: 239917
* [Hexagon] Adding MC ELF streamer and updating addend relocation test which ↵Colin LeMahieu2015-06-171-1/+1
| | | | | | shows correct ELF symbol. llvm-svn: 239876
* [Hexagon] Using readobj rather than objdump.Colin LeMahieu2015-06-151-1/+1
| | | | llvm-svn: 239770
* [Hexagon] PC-relative offsets are relative to packet start rather than the ↵Colin LeMahieu2015-06-151-0/+10
| | | | | | offset of the relocation. Set relocation addend and check it's correct in the ELF. llvm-svn: 239769
* [Hexagon] Adding some codegen tests and updating some to match spec.Colin LeMahieu2015-06-1312-21/+350
| | | | llvm-svn: 239690
* [Hexagon] Making intrinsic tests agnostic to register allocation. Narrowing ↵Colin LeMahieu2015-06-1211-749/+777
| | | | | | intrinsic parameters to appropriate width. llvm-svn: 239634
* [Hexagon] Adding decoders for signed operands and ensuring all signed ↵Colin LeMahieu2015-06-101-0/+99
| | | | | | operand types disassemble correctly. llvm-svn: 239477
* [Hexagon] Adding functionality for searching for compound instruction pairs. ↵Colin LeMahieu2015-06-081-0/+17
| | | | | | Compound instructions reduce slot resource requirements freeing those packet slots up for more instructions. llvm-svn: 239307
* [Hexagon] Reapply r239097 with tests corrected for shuffling and duplexing.Colin LeMahieu2015-06-055-87/+20
| | | | llvm-svn: 239161
* Shouldn't be XFAIL'ed.Colin LeMahieu2015-06-041-1/+0
| | | | llvm-svn: 239103
* Revert r239095 incorrect test tree.Colin LeMahieu2015-06-042-7/+1
| | | | llvm-svn: 239102
* [Hexagon] Adding functionality for duplexing. Duplexing is a way to ↵Colin LeMahieu2015-06-041-0/+7
| | | | | | compress commonly used pairs of instructions in order to reduce code size. The test case duplex.ll normally would be 8 bytes, assign register to 0 and jump to link register. After duplexing this is only 4 bytes. This also tests the HexagonMCShuffler code path which is used to make sure duplexed instructions still follow slot requirements. llvm-svn: 239095
* [Hexagon] Test doesn't work on all platforms. At any rate the uninitialized ↵Colin LeMahieu2015-06-031-7/+0
| | | | | | variable issue was fixed. Removing re-registering ASM backend. llvm-svn: 238949
* [Hexagon] Reapply 238772 OSABI was not correctly set, added empty_elf test ↵Colin LeMahieu2015-06-032-0/+21
| | | | | | to make sure it is. llvm-svn: 238947
* Revert "[Hexagon] Adding basic ELF relocation generation and testing ↵Rafael Espindola2015-06-011-14/+0
| | | | | | | | | | | | advanced relaxation codepath." This reverts commit r238748. It broke the msan bot: http://lab.llvm.org:8011/builders/sanitizer-x86_64-linux-fast/builds/4372/steps/check-llvm%20msan/logs/stdio llvm-svn: 238772
* [Hexagon] Adding basic ELF relocation generation and testing advanced ↵Colin LeMahieu2015-06-011-0/+14
| | | | | | relaxation codepath. llvm-svn: 238748
* [Hexagon] Disassembling, printing, and emitting instructions a whole-bundle ↵Colin LeMahieu2015-05-292-0/+2
| | | | | | at a time which is the semantic unit for Hexagon. Fixing tests to use the new format. Disabling tests in the direct object emission path for a followup patch. llvm-svn: 238556
* [Hexagon] Generate hardware loop for a vectorized loopBrendon Cahoon2015-05-141-0/+93
| | | | | | | | | The induction variable in the vectorized loop wasn't recognized properly, so a hardware loop wasn't generated. Differential Revision: http://reviews.llvm.org/D9722 llvm-svn: 237388
* [Hexagon] Remove dead constant assignment in hardware loop passBrendon Cahoon2015-05-141-0/+23
| | | | | | | | | | | After converting a loop to a hardware loop, the pass should remove any unnecessary instructions from the old compare-and-branch code. This patch removes a dead constant assignment that was used in the compare instruction. Differential Revision: http://reviews.llvm.org/D9720 llvm-svn: 237373
* [Hexagon] Check for underflow/wrap in hardware loop passBrendon Cahoon2015-05-144-0/+198
| | | | | | | | If the loop trip count may underflow or wrap, the compiler should not generate a hardware loop since the trip count will be incorrect. llvm-svn: 237365
* [Hexagon] Generate loop1 instruction for nested loopsBrendon Cahoon2015-05-131-0/+68
| | | | | | | | loop1 is for the outer loop and loop0 is for the inner loop. Differential Revision: http://reviews.llvm.org/D9680 llvm-svn: 237266
* [Hexagon] Generate hardware loop when loop has a critical edgeBrendon Cahoon2015-05-131-0/+58
| | | | | | | | | The hardware loop pass should try to generate a hardware loop instruction when the original loop has a critical edge. Differential Revision: http://reviews.llvm.org/D9678 llvm-svn: 237258
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