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* [Hexagon] Simplify A4_rcmp[n]eqi R, 0Krzysztof Parzyszek2018-07-301-0/+154
| | | | | | | Consider cases when register R is known to be zero/non-zero, or when it is defined by a C2_muxii instruction. llvm-svn: 338251
* [Hexagon] Properly scale bit index when extracting elements from vNi1Krzysztof Parzyszek2018-07-251-0/+18
| | | | | | | | For example v = <2 x i1> is represented as bbbbaaaa in a predicate register, where b = v[1], a = v[0]. Extracting v[1] is equivalent to extracting bit 4 from the predicate register. llvm-svn: 337934
* [Hexagon] Handle unnamed globals in HexagonConstExprKrzysztof Parzyszek2018-07-231-0/+38
| | | | | | Instead of comparing names, compare positions in the parent module. llvm-svn: 337723
* [Hexagon] Disable packets in test to avoid ordering issues in checksKrzysztof Parzyszek2018-07-201-2/+2
| | | | llvm-svn: 337624
* [Hexagon] Avoid introducing calls into coalesced range of HVX vector pairsKrzysztof Parzyszek2018-07-131-0/+26
| | | | | | | | | | | | | If an HVX vector register is to be coalesced into a vector pair, make sure that the vector pair will not have a function call in its live range, unless it already had one. All HVX vector registers are volatile, so any vector register live across a function call will have to be spilled. If a vector needs to be spilled, and it's coalesced into a vector pair then the whole pair will need to be spilled (even if only a part of it is live), taking extra stack space. llvm-svn: 337073
* [Hexagon] Change .mir testcase to make sure function is not in SSA formKrzysztof Parzyszek2018-07-101-0/+1
| | | | | | | | | If a machine function satisfies SSA, the IsSSA property is assumed even if the pass to be executed runs after existing from SSA. If the pass output then does not conform to SSA, a verifier error will be flagged (with expensive checks enabled). llvm-svn: 336682
* [Hexagon] Add implicit uses even when untied explicit uses are presentKrzysztof Parzyszek2018-07-101-0/+24
| | | | | | | | | | | | | | | | | | An explicit untied use is not sufficient to maintain liveness of a register redefined in a predicated instruction. For example %1 = COPY %0 ... %1 = A2_paddif %2, %1, 1 could become $r1 = COPY $r0 ... $r1 = A2_paddif $p0, $r1, 1 and later $r1 = COPY $r0 ;; this is not really dead! ... $r1 = A2_paddif $p0, $r0, 1 llvm-svn: 336662
* [DAGCombiner] Ensure we use the correct CC result type in visitSDIV (REAPPLIED)Simon Pilgrim2018-06-281-0/+14
| | | | | | | | | | We could get away with it for constant folded cases, but not for rL335719. Thanks to Krzysztof Parzyszek for noticing. Reapply original commit rL335821 which was reverted at rL335871 due to a WebAssembly bug that was fixed at rL335884. llvm-svn: 335886
* Revert "[DAGCombiner] Ensure we use the correct CC result type in visitSDIV"Haojian Wu2018-06-281-14/+0
| | | | | | | | This reverts commit r335821. This crashes the webassembly test, run "ninja check-llvm-codegen-webassembly" to reproduce. llvm-svn: 335871
* [DAGCombiner] Ensure we use the correct CC result type in visitSDIVSimon Pilgrim2018-06-281-0/+14
| | | | | | | | We could get away with it for constant folded cases, but not for rL335719. Thanks to Krzysztof Parzyszek for noticing. llvm-svn: 335821
* [Hexagon] Add a "generic" cpuBrendon Cahoon2018-06-261-0/+7
| | | | | | | | | | Add the generic processor for Hexagon so that it can be used with 3rd party programs that create a back-end with the "generic" CPU. This patch also enables the JIT for Hexagon. Differential Revision: https://reviews.llvm.org/D48571 llvm-svn: 335641
* [Hexagon] Replace .ll test for expanding post-ra pesudos with .mirKrzysztof Parzyszek2018-06-202-53/+14
| | | | llvm-svn: 335158
* [Hexagon] Enforce restrictions on packetizing cache instructionsKrzysztof Parzyszek2018-06-191-0/+16
| | | | llvm-svn: 335061
* Remove <undef> from rematerialized full registerKrzysztof Parzyszek2018-06-151-0/+37
| | | | | | | | | | | When coalescing a small register into a subregister of a larger register, if the larger register is rematerialized, the function updateRegDefUses can add an <undef> flag to the rematerialized definition (since it's treating it as only definining the coalesced subregister). While with that assumption doing so is not incorrect, make sure to remove the flag later on after the call to updateRegDefUses. llvm-svn: 334845
* [DAGCombiner] Recognize more patterns for ABSKrzysztof Parzyszek2018-06-121-1/+27
| | | | | | Differential Revision: https://reviews.llvm.org/D47831 llvm-svn: 334553
* [Hexagon] Make floating point operations expensive for vectorizationKrzysztof Parzyszek2018-06-121-0/+91
| | | | llvm-svn: 334508
* [SelectionDAG] Provide default expansion for rotatesKrzysztof Parzyszek2018-06-122-2/+207
| | | | | | | | | | | | | Implement default legalization of rotates: either in terms of the rotation in the opposite direction (if legal), or in terms of shifts and ors. Implement generating of rotate instructions for Hexagon. Hexagon only supports rotates by an immediate value, so implement custom lowering of ROTL/ROTR on Hexagon. If a rotate is not legal, use the default expansion. Differential Revision: https://reviews.llvm.org/D47725 llvm-svn: 334497
* [Hexagon] Late predicate producers cannot be used as dot-new sourcesKrzysztof Parzyszek2018-06-111-0/+26
| | | | llvm-svn: 334426
* [Hexagon] Implement vector-pair zero as V6_vsubw_dvKrzysztof Parzyszek2018-06-061-0/+41
| | | | llvm-svn: 334123
* [Hexagon] Split CTPOP of vector pairsKrzysztof Parzyszek2018-06-061-0/+26
| | | | llvm-svn: 334109
* [Hexagon] Add pattern to generate 64-bit neg instructionKrzysztof Parzyszek2018-06-052-14/+17
| | | | llvm-svn: 334043
* [Hexagon] Add more patterns for generating abs/absp instructionsKrzysztof Parzyszek2018-06-052-14/+57
| | | | llvm-svn: 334038
* [Hexagon] Select HVX code for vector CTPOP, CTLZ, and CTTZKrzysztof Parzyszek2018-06-012-0/+249
| | | | llvm-svn: 333760
* [SelectionDAG] Expand UADDO/USUBO into ADD/SUBCARRY if legal for targetKrzysztof Parzyszek2018-06-013-53/+25
| | | | | | | | | Additionally, implement handling of ADD/SUBCARRY on Hexagon, utilizing the UADDO/USUBO expansion. Differential Revision: https://reviews.llvm.org/D47559 llvm-svn: 333751
* [Hexagon] Use vector align-left when shift amount fits in 3 bitsKrzysztof Parzyszek2018-05-304-56/+28
| | | | | | | This saves an instruction because for align-right the shift amount would need to be put in a register first. llvm-svn: 333543
* [Hexagon] Fix packing source vectors in shufflevector selection Krzysztof Parzyszek2018-05-251-0/+12
| | | | | | | | When the shuffle mask selected a subvector of the second input vector, and aligning of the source was performed, the shuffle mask was updated incorrectly, resulting in an ICE further in the selection process. llvm-svn: 333279
* [Hexagon] Add patterns for accumulating HVX comparesKrzysztof Parzyszek2018-05-224-72/+651
| | | | llvm-svn: 333009
* [Hexagon] Generate post-increment for floating point typesBrendon Cahoon2018-05-182-2/+87
| | | | | | | | | | The code that generates post-increments for Hexagon considered integer values only. This patch adds support to generate them for floating point values, f32 and f64. Differential Revision: https://reviews.llvm.org/D47036 llvm-svn: 332748
* [Hexagon] preserve test intent by removing undefSanjay Patel2018-05-161-3/+3
| | | | | | | | | | | | We need to clean up the DAG floating-point undef logic. This process is similar to how we handled integer undef logic in D43141. And as we did there, I'm trying to reduce the patch by changing tests that would probably become meaningless once we correct FP undef folding. llvm-svn: 332550
* [Hexagon] Mark HVX vector predicate bitwise ops as legal, add patternsKrzysztof Parzyszek2018-05-162-0/+204
| | | | llvm-svn: 332525
* [Hexagon] Remove unused flag from subtarget and (non)corresponding testKrzysztof Parzyszek2018-05-151-26/+0
| | | | llvm-svn: 332365
* [Hexagon] Add a target feature for memop generationKrzysztof Parzyszek2018-05-141-0/+23
| | | | llvm-svn: 332285
* Hexagon: Put relocations after instructions not packets.Sid Manning2018-05-141-1/+1
| | | | | | | | | | | | | Change relocation output so that relocation information follows individual instructions rather than clustering them at the end of packets. This change required shifting block of code but the actual change is in HexagonPrettyPrinter's PrintInst. Differential Revision: https://reviews.llvm.org/D46728 llvm-svn: 332283
* [Hexagon] Avoid predicate copies to integer registers from store-lockedKrzysztof Parzyszek2018-05-143-7/+7
| | | | llvm-svn: 332260
* [Hexagon] Add patterns for vector shift-and-accumulateKrzysztof Parzyszek2018-05-092-432/+65
| | | | llvm-svn: 331918
* [DebugInfo] Add DILabel metadata and intrinsic llvm.dbg.label.Shiva Chen2018-05-0911-13/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In order to set breakpoints on labels and list source code around labels, we need collect debug information for labels, i.e., label name, the function label belong, line number in the file, and the address label located. In order to keep these information in LLVM IR and to allow backend to generate debug information correctly. We create a new kind of metadata for labels, DILabel. The format of DILabel is !DILabel(scope: !1, name: "foo", file: !2, line: 3) We hope to keep debug information as much as possible even the code is optimized. So, we create a new kind of intrinsic for label metadata to avoid the metadata is eliminated with basic block. The intrinsic will keep existing if we keep it from optimized out. The format of the intrinsic is llvm.dbg.label(metadata !1) It has only one argument, that is the DILabel metadata. The intrinsic will follow the label immediately. Backend could get the label metadata through the intrinsic's parameter. We also create DIBuilder API for labels to be used by Frontend. Frontend could use createLabel() to allocate DILabel objects, and use insertLabel() to insert llvm.dbg.label intrinsic in LLVM IR. Differential Revision: https://reviews.llvm.org/D45024 Patch by Hsiangkai Wang. llvm-svn: 331841
* [Hexagon] Handle non-immediate constants in HexagonSplitDoubleKrzysztof Parzyszek2018-05-041-0/+24
| | | | llvm-svn: 331527
* [Hexagon] Skip reserved physical registers when updating livenessKrzysztof Parzyszek2018-05-041-0/+30
| | | | llvm-svn: 331518
* [LivePhysRegs] Remove registers clobbered by regmasks from the live setKrzysztof Parzyszek2018-04-301-0/+39
| | | | | | | | Dead defs were being removed from the live set (in stepForward), but registers clobbered by regmasks weren't (more specifically, they were actually removed by removeRegsInMask, but then they were added back in). llvm-svn: 331219
* [Hexagon] Improve HVX instruction selection (bitcast, vsplat)Krzysztof Parzyszek2018-04-202-0/+76
| | | | | | | | | | There was some unfortunate interaction between VSPLAT and BITCAST related to the selection of constant vectors (coming from selecting shuffles). Introduce VSPLATW that always splats a 32-bit word, and can have arbitrary result type (to avoid BITCASTs of VSPLAT). Clean up the previous selection of BITCAST/VSPLAT. llvm-svn: 330471
* [Hexagon] Skip fixed-stack indexes in HexagonConstExtendersKrzysztof Parzyszek2018-04-201-0/+51
| | | | | | | Fixed slots have negative values, and TRI::stackSlot2Index and TRI::index2StackSlot do not handle negative numbers. llvm-svn: 330468
* [if-converter] Handle BBs that terminate in ret during diamond conversionKrzysztof Parzyszek2018-04-191-0/+25
| | | | | | | | | | This fixes https://llvm.org/PR36825. Original patch by Valentin Churavy (D45218). Differential Revision: https://reviews.llvm.org/D45731 llvm-svn: 330345
* [Hexagon] Use legal types when lowering CONCAT_VECTORS via BUILD_VECTORKrzysztof Parzyszek2018-04-191-0/+34
| | | | llvm-svn: 330344
* [Hexagon] Generate code for vector bswap intrinsicsKrzysztof Parzyszek2018-04-191-0/+45
| | | | llvm-svn: 330333
* [Hexagon] Add/fix patterns for 32/64-bit vector compares and logical opsKrzysztof Parzyszek2018-04-194-3/+356
| | | | llvm-svn: 330330
* [Hexagon] Do not merge initializers for stack and non-stack expressionsKrzysztof Parzyszek2018-04-171-0/+35
| | | | | | | | | Stack addressing needs addressing modes that provide an offset field immediately following the frame index. An initializer from a non-stack addressing could force the stack address to use a form that does not provide an offset field. llvm-svn: 330191
* Disable flaky tests till they get fixed.Galina Kistanova2018-04-102-1/+2
| | | | llvm-svn: 329763
* [Hexagon] Handle subregisters when calculating iteration count in HW loopsKrzysztof Parzyszek2018-04-061-0/+30
| | | | llvm-svn: 329434
* [Hexagon] Remove unneeded attributes from lit testKrzysztof Parzyszek2018-04-031-1/+1
| | | | llvm-svn: 329078
* [Hexagon] Fix testcaseKrzysztof Parzyszek2018-03-301-1/+1
| | | | llvm-svn: 328899
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